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litex/test
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Florent Kermarrec 4990bf33c0 soc/core: simplify/cleanup HyperRAM core 
- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).

Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
 		2019-08-16 14:04:58 +02:00
..
__init__.py add test directory with test_code_8b10b.py (from misoc) 2017-04-24 18:46:55 +02:00
test_axi.py test/test_axi: remove use of rand_wait, rename rand_level to random 2019-07-23 21:02:09 +02:00
test_bitbang.py cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging 2019-07-05 14:26:10 +02:00
test_code_8b10b.py test: add copyright header 2019-06-23 23:31:11 +02:00
test_csr.py test: add copyright header 2019-06-23 23:31:11 +02:00
test_ecc.py soc/cores: add ECC (Error Correcting Code) 2019-07-13 11:44:29 +02:00
test_gearbox.py test: add copyright header 2019-06-23 23:31:11 +02:00
test_hyperbus.py soc/core: simplify/cleanup HyperRAM core 2019-08-16 14:04:58 +02:00
test_icap.py cores: add ICAP core (tested with reconfiguration commands) 2019-07-05 18:30:34 +02:00
test_prbs.py test: add copyright header 2019-06-23 23:31:11 +02:00
test_spi.py cores/spi: rename add_control paramter to add_csr 2019-07-20 12:56:37 +02:00
test_targets.py boards: community supported boards are now located at https://github.com/litex-hub/litex-boards 2019-06-24 12:05:02 +02:00