Navaneeth Bhardwaj c1c9dc456c Fix WID in axi versions ... There is no WID in AXI4		2022-12-29 12:34:49 +05:30
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build	build/altera: Fix IP integration	2022-12-23 16:51:35 +01:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	gen/fhdl/module: Add add/get_module methods to simplify user design and avoid direct use of setattr/getattr.	2022-12-08 14:20:38 +01:00
soc	Fix WID in axi versions	2022-12-29 12:34:49 +05:30
tools	tools/litex_cli: Fix --write.	2022-12-12 11:26:37 +01:00
__init__.py	colorer: Avoid duplication and move it to litex/gen.	2022-11-03 09:49:51 +01:00