litex/litex/soc
2019-04-28 23:40:33 +02:00
..
cores cpu: integrate nmigen version of Minerva, add submodule 2019-04-28 23:40:33 +02:00
integration Adding testing of cpu variants. 2019-04-26 18:57:49 -05:00
interconnect soc/interconnect/axi: add AXIBurst2Beat 2019-04-19 12:13:16 +02:00
software software/libnet/microudp: rearrange send_packet, add comments and remove txlen padding 2019-04-24 11:32:40 +02:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
MISOC_LICENSE litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00