Florent Kermarrec 9cbed91b3e soc/interconnect/axi: add AXIBurst2Beat ... Converts AXI bursts commands to AXI beats.		2019-04-19 12:13:16 +02:00
..
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
avalon.py	soc/interconnect/avalon: add description	2019-04-19 11:43:15 +02:00
axi.py	soc/interconnect/axi: add AXIBurst2Beat	2019-04-19 12:13:16 +02:00
axi_lite.py	test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified)	2019-02-27 22:24:56 +01:00
csr.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
csr_bus.py	soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another)	2018-07-10 13:29:32 +02:00
csr_eventmanager.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
stream.py	soc/interconnect/stream: add support for buffered async fifo	2018-12-08 01:24:08 +01:00
stream_packet.py	soc/interconnect/stream_packet: use reverse_bytes from litex.gen	2018-10-30 10:16:55 +01:00
stream_sim.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
wishbone.py	soc/integration/soc_core: allow disabling wishbone timeout	2019-01-29 12:47:11 +01:00
wishbone2csr.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
wishbonebridge.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00