Sebastien Bourdeauducq dcedc4e6a5 actorlib/structuring/Pipeline: make 'busy' a signal		2014-11-01 21:48:02 +08:00
..
actorlib	actorlib/structuring/Pipeline: make 'busy' a signal	2014-11-01 21:48:02 +08:00
bank	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
bus	bus/csr: add configurable address_width (needed more than 32 modules with CSR)	2014-11-01 21:22:11 +08:00
fhdl	fhdl/verilog: fix tristate to instance connection	2014-10-29 18:18:17 +08:00
flow	flow/actor, actorlib/structuring: add packet support	2014-11-01 21:22:46 +08:00
genlib	crc: generate error asynchronously to avoid stalling the flow and simplify	2014-11-01 21:21:46 +08:00
pytholite	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
sim	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
test	genlib/fifo: add replace command to sync FIFO	2014-09-10 21:19:15 +08:00
util	utils/misc: add gcd_multiple function to compute GCD or any number of integers	2013-12-12 17:36:50 +01:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00