Sebastien Bourdeauducq df1ed32765 genlib/record/connect: add match_by_position		2013-04-10 21:33:45 +02:00
..
actorlib	flow: use Module and new Record APIs	2013-04-10 19:12:42 +02:00
bank	New CSR API	2013-03-30 17:28:41 +01:00
bus	bus: replace simple bus module with new bidirectional Record	2013-04-01 21:54:21 +02:00
fhdl	fhdl/module/finalize: pass additional args to do_finalize	2013-03-30 11:29:46 +01:00
flow	flow: use Module and new Record APIs	2013-04-10 19:12:42 +02:00
genlib	genlib/record/connect: add match_by_position	2013-04-10 21:33:45 +02:00
pytholite	flow: use Module and new Record APIs	2013-04-10 19:12:42 +02:00
sim	sim: remove PureSimulable (superseded by Module)	2013-03-15 19:41:30 +01:00
uio	flow: use Module and new Record APIs	2013-04-10 19:12:42 +02:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00