Florent Kermarrec eab5161d47 boards: keep in sync with LiteX-boards		2020-02-27 11:18:14 +01:00
..
boards	boards: keep in sync with LiteX-boards	2020-02-27 11:18:14 +01:00
build	build/sim: add Verilator FST tracing support.	2020-02-20 13:53:31 +01:00
gen	gen/fhdl/verilog: fix signed init values	2020-01-12 22:06:35 +01:00
soc	interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests)	2020-02-26 15:13:29 +01:00
tools	tools: litex_gen: fix missing UART pins	2020-02-25 14:24:29 +01:00
__init__.py	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00