Florent Kermarrec ed12f8787d litex/gen: Add some comments.		2023-07-27 16:18:30 +02:00
..
fhdl	gen/fhdl/module: Fix CSR clock domain renaming to cores converted to LiteXModule, thanks @smunaut.	2023-07-14 10:01:32 +02:00
genlib	gen/genlib/cdc: Add missing import.	2023-07-07 11:51:04 +02:00
sim	gen/fhdl: Integrate namer from Migen to give us more flexibility on generated verilog names.	2022-05-06 16:04:24 +02:00
__init__.py	litex/gen: Split common in common/context/reduce/signal.	2023-07-27 15:02:37 +02:00
common.py	litex/gen: Add some comments.	2023-07-27 16:18:30 +02:00
context.py	litex/gen: Add some comments.	2023-07-27 16:18:30 +02:00
reduce.py	litex/gen: Split common in common/context/reduce/signal.	2023-07-27 15:02:37 +02:00
signal.py	litex/gen: Add some comments.	2023-07-27 16:18:30 +02:00