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f0993ea422
litex
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liteeth
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core
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Florent Kermarrec
9f91348c1c
udp/crossbar: add possibility to get port with dw != 8 (16, 32, 64, ...)
2015-02-10 11:22:23 +01:00
..
arp
improve RX timings (make valid synchronous)
2015-02-09 15:04:04 +01:00
etherbone
etherbone: add skeleton
2015-02-09 22:37:41 +01:00
icmp
icmp: replace fifo with packet buffer and reduce buffering
2015-02-09 19:24:49 +01:00
ip
udp/crossbar: add possibility to get port with dw != 8 (16, 32, 64, ...)
2015-02-10 11:22:23 +01:00
udp
udp/crossbar: add possibility to get port with dw != 8 (16, 32, 64, ...)
2015-02-10 11:22:23 +01:00
__init__.py
udp: add crossbar
2015-02-09 11:59:36 +01:00