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litex/misoclib/mem/sdram
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Florent Kermarrec f40140dba5 sdram: refactor minicon and fix issues with DDRx memories 
- simplify code
- fix AddressSlicer
- manage write latency and write to precharge timings
- add odt/reset_n signals
2015-05-29 12:31:56 +02:00
..
core sdram: refactor minicon and fix issues with DDRx memories 2015-05-29 12:31:56 +02:00
frontend global: more pep8 2015-04-13 18:02:26 +02:00
phy global: more pep8 2015-04-13 18:02:26 +02:00
test global: more pep8 2015-04-13 18:02:26 +02:00
__init__.py global: pep8 (replace tabs with spaces) 2015-04-13 16:19:55 +02:00
module.py global: pep8 (E302) 2015-04-13 16:47:22 +02:00