Florent Kermarrec f40140dba5 sdram: refactor minicon and fix issues with DDRx memories ... - simplify code - fix AddressSlicer - manage write latency and write to precharge timings - add odt/reset_n signals		2015-05-29 12:31:56 +02:00
..
flash	spiflash: fix miso bitbang with large DQ	2015-05-06 00:05:25 +08:00
litesata	litesata: more doc fixes	2015-05-26 14:13:13 +08:00
sdram	sdram: refactor minicon and fix issues with DDRx memories	2015-05-29 12:31:56 +02:00
__init__.py	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00