Florent Kermarrec
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f40140dba5
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sdram: refactor minicon and fix issues with DDRx memories
- simplify code
- fix AddressSlicer
- manage write latency and write to precharge timings
- add odt/reset_n signals
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2015-05-29 12:31:56 +02:00 |
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Florent Kermarrec
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2ccb5655c9
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global: more pep8
we will have to continue the work... volunteers are welcome :)
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2015-04-13 18:02:26 +02:00 |
|
Florent Kermarrec
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fc68d915c1
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global: pep8 (E261, E271)
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2015-04-13 17:16:12 +02:00 |
|
Florent Kermarrec
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f3c010c1d5
|
global: pep8 (E225)
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2015-04-13 17:01:05 +02:00 |
|
Florent Kermarrec
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796119fcaf
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global: pep8 (E203)
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2015-04-13 16:53:07 +02:00 |
|
Florent Kermarrec
|
ca7019fa0d
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global: pep8 (E231)
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2015-04-13 16:51:00 +02:00 |
|
Florent Kermarrec
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9ad90b531e
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global: pep8 (E201)
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2015-04-13 16:48:51 +02:00 |
|
Florent Kermarrec
|
f68423f423
|
global: pep8 (E302)
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2015-04-13 16:47:22 +02:00 |
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Florent Kermarrec
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d9e09707ae
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global: pep8 (replace tabs with spaces)
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2015-04-13 16:19:55 +02:00 |
Robert Jordens
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d6c19858fa
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s6ddrphy: redo phase_sel, get rid of CLOCK_DEDICATED_ROUTE
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2015-04-10 16:12:29 +08:00 |
Sebastien Bourdeauducq
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382ed013af
|
minor cleanups
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2015-04-02 14:40:29 +08:00 |
|
Florent Kermarrec
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b313772a0c
|
sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0)
|
2015-03-29 12:34:40 +02:00 |
|
Florent Kermarrec
|
a8d91c0c1d
|
sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue)
|
2015-03-28 16:35:15 +01:00 |
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Florent Kermarrec
|
75ee8a5db9
|
sdram/phy/simphy: OK with DDR3
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2015-03-28 01:59:55 +01:00 |
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Florent Kermarrec
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51ce7cad6f
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sdram/phy/simphy: expose settings to user and test with DDR/LPDDR/DDR2
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2015-03-28 01:18:35 +01:00 |
|
Florent Kermarrec
|
a95b3f8f13
|
sdram/core/lasmicon: add enabled parameter to refresher (for some simulations we need to disable it)
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2015-03-28 01:17:50 +01:00 |
|
Florent Kermarrec
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7fe748e1b0
|
sdram/module: clean up tREFI. (use 64ms/8k or 4k)
|
2015-03-28 01:09:21 +01:00 |
|
Florent Kermarrec
|
9137b91e9e
|
sdram: remove nbits from modules and databits from GeomSettings
|
2015-03-26 23:27:37 +01:00 |
|
Florent Kermarrec
|
9a9af17aca
|
sdram/phy/simphy: remove use of iter
|
2015-03-26 23:02:23 +01:00 |
|
Florent Kermarrec
|
e6de4b1bf9
|
sdram/phy: add simphy (software memtest OK in simulation with MT48LC4M16)
|
2015-03-26 22:28:32 +01:00 |
|
Florent Kermarrec
|
257706517e
|
software/memtest: remove Mixxeo/M1 hardcoded values in bandwidth computation
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2015-03-26 00:01:42 +01:00 |
|
Florent Kermarrec
|
ff11cb97a9
|
sdram/core/lasmicon: automatically insert bandwidth module when with_memtest is True
|
2015-03-25 17:22:26 +01:00 |
|
Florent Kermarrec
|
ba8b24df57
|
sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy
|
2015-03-25 16:57:38 +01:00 |
|
Florent Kermarrec
|
7ea9e2ba89
|
sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings.
|
2015-03-25 16:56:29 +01:00 |
|
Florent Kermarrec
|
92f81409f2
|
sdram/module: fix tREFI on AS4C16M16
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2015-03-22 03:20:02 +01:00 |
|
Florent Kermarrec
|
30c2521eb0
|
sdram: pass sdram_controller_settings to SDRAMSoC
|
2015-03-21 23:12:18 +01:00 |
|
Florent Kermarrec
|
70469e1f37
|
sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit)
|
2015-03-21 21:32:39 +01:00 |
|
Florent Kermarrec
|
c60d99583d
|
sdram/module: add tREFI uniformization to TODO
|
2015-03-21 18:59:16 +01:00 |
|
Florent Kermarrec
|
0f9b0c6f0f
|
sdram/module: add MT47H128M8 DDR2 (used for a customer)
|
2015-03-21 18:52:10 +01:00 |
|
Florent Kermarrec
|
45eb5090db
|
sdram/module: add speedgrate note for IS42S16160 and AS4C16M16
|
2015-03-21 18:41:59 +01:00 |
|
Florent Kermarrec
|
a560ba35bd
|
sdram/module: add AS4C16M16 for minispartan6
|
2015-03-21 18:38:53 +01:00 |
|
Florent Kermarrec
|
854058a8db
|
sdram/module: add description and TODO list
|
2015-03-21 17:44:04 +01:00 |
|
Florent Kermarrec
|
52924ee1f2
|
sdram: define MT46V32M16/MT8JTF12864 and use it on pipistrello/kc705
|
2015-03-21 17:25:36 +01:00 |
|
Florent Kermarrec
|
fd2f8d4bb4
|
sdram: define MT46V32M16 and use it on m1/mixxeo
|
2015-03-21 17:04:58 +01:00 |
|
Florent Kermarrec
|
de2f1c31d5
|
sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets
|
2015-03-21 16:56:53 +01:00 |
|
Florent Kermarrec
|
6e4b7c6cfd
|
sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
|
2015-03-21 12:55:39 +01:00 |
|
Florent Kermarrec
|
905be50451
|
sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy
|
2015-03-03 09:55:25 +01:00 |
|
Florent Kermarrec
|
9210272356
|
sdram: pass phy_settings to LASMIcon, MiniCON and init_sequence
|
2015-03-03 09:23:21 +01:00 |
|
Florent Kermarrec
|
2f7206b386
|
sdram: revert use of scalar values for DFIInjector
|
2015-03-03 09:09:54 +01:00 |
|
Florent Kermarrec
|
9df60bf98e
|
lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True)
|
2015-03-03 09:02:53 +01:00 |
|
Florent Kermarrec
|
410a162841
|
sdram: disable by default bandwidth_measurement on lasmicon
|
2015-03-02 19:53:16 +01:00 |
|
Florent Kermarrec
|
473997df26
|
cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
|
2015-03-02 16:52:17 +01:00 |
|
Florent Kermarrec
|
8280acd3a7
|
sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core
|
2015-03-02 12:17:49 +01:00 |
|
Florent Kermarrec
|
3465db25a7
|
soc/sdram: be more generic in naming
|
2015-03-02 11:55:28 +01:00 |
|
Florent Kermarrec
|
97331153e0
|
sdram: create core dir and move lasmicon/minicon in it
|
2015-03-02 11:38:22 +01:00 |
|
Florent Kermarrec
|
de698c51e4
|
sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner)
|
2015-03-02 11:29:43 +01:00 |
|
Florent Kermarrec
|
6b24562eea
|
sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)
|
2015-03-02 10:59:43 +01:00 |
|
Florent Kermarrec
|
46020fd253
|
sdram: for now revert dat_ack change (it seems there is an small issue, will have a closer look)
|
2015-03-02 10:34:29 +01:00 |
|
Florent Kermarrec
|
c0b38e4905
|
sdram/lasmicon: create a separate file for the crossbar and remove it from lasmibus
|
2015-03-02 09:18:32 +01:00 |
|
Florent Kermarrec
|
7300879b7f
|
sdram: move dfii to phy
|
2015-03-02 09:08:28 +01:00 |