Florent Kermarrec 8d1c555e36 misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq. ... An optimal solution for both sync and async mode is not easy to implement, it would requires moving CDC out of UART module and handling in the PHY with AsyncFIFO or minimal depth. For now use the solution that works for both cases. We'll try to optimize that if we have performance issues.		2015-07-25 00:25:09 +02:00
..
liteeth	liteeth/core: add with_icmp parameter	2015-07-06 21:31:20 +02:00
litepcie	litepcie/frontend/dma: group loop index and count in loop_status register (avoid 2 register reads)	2015-07-24 13:52:57 +02:00
liteusb	liteusb/core/packet: fix missing ,	2015-05-25 13:53:02 +02:00
spi	global: pep8 (W262)	2015-04-13 17:02:59 +02:00
uart	misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq.	2015-07-25 00:25:09 +02:00
__init__.py	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00
gpio.py	cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)	2015-05-02 16:22:33 +02:00