Florent Kermarrec f58394f6af soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)		2015-03-01 18:25:47 +01:00
..
com	soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)	2015-03-01 18:25:47 +01:00
cpu	litescope: create example design derived from SoC that can be used on all targets	2015-02-28 22:19:24 +01:00
mem	flash/spi: make bitbang optional (enabled by default)	2015-03-01 17:15:22 +01:00
others	move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future)	2015-02-28 11:51:51 +01:00
soc	soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)	2015-03-01 18:25:47 +01:00
tools	uart: use data instead of d on endpoint's layouts (coherency with others cores)	2015-03-01 16:56:48 +01:00
video	video: reintegrate dvisampler from mixxeo (DVI/HDMI interfaces are common in today's SoCs)	2015-03-01 10:07:52 +01:00
__init__.py	rename milkymist-ng to MiSoC	2013-11-09 15:27:32 +01:00