Florent Kermarrec f58394f6af soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)		2015-03-01 18:25:47 +01:00
..
liteeth	liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen	2015-03-01 16:48:41 +01:00
liteusb	liteXXX cores: update README and doc	2015-02-28 21:40:59 +01:00
spi	misoclib/com: add spi (only SPIMaster for now)	2015-02-28 09:43:03 +01:00
uart	soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)	2015-03-01 18:25:47 +01:00
__init__.py	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00