Sebastien Bourdeauducq f69674e89c interconnect: add bus/bank components from Migen		2015-09-24 20:48:18 +08:00
..
__init__.py	interconnect: add bus/bank components from Migen	2015-09-24 20:48:18 +08:00
csr.py	interconnect: add bus/bank components from Migen	2015-09-24 20:48:18 +08:00
csr_bus.py	interconnect: add bus/bank components from Migen	2015-09-24 20:48:18 +08:00
csr_eventmanager.py	interconnect: add bus/bank components from Migen	2015-09-24 20:48:18 +08:00
dfi.py	break down sdram, improve consistency of core names	2015-09-24 15:59:55 +08:00
dma_lasmi.py	break down sdram, improve consistency of core names	2015-09-24 15:59:55 +08:00
lasmi_bus.py	interconnect: add bus/bank components from Migen	2015-09-24 20:48:18 +08:00
lasmi_xbar.py	interconnect: add bus/bank components from Migen	2015-09-24 20:48:18 +08:00
wishbone.py	interconnect: add bus/bank components from Migen	2015-09-24 20:48:18 +08:00
wishbone2csr.py	interconnect: add bus/bank components from Migen	2015-09-24 20:48:18 +08:00
wishbone2lasmi.py	break down sdram, improve consistency of core names	2015-09-24 15:59:55 +08:00