litex/migen/bus
Florent Kermarrec e82531cdf8 move dfi/lasmibus/wishbone2lasmi to MiSoC sdram 2015-02-27 16:54:22 +01:00
..
__init__.py
csr.py bus/csr: add configurable address_width (needed more than 32 modules with CSR) 2014-11-01 21:22:11 +08:00
memory.py New simulation API 2014-01-26 22:19:43 +01:00
transactions.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
wishbone.py Wishbone DownConverter: Fix sel signal 2014-11-26 19:33:12 +08:00
wishbone2csr.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00