Sebastien Bourdeauducq ff29c86fe1 litesata/kc705: use FMC pin names		2015-03-03 01:02:50 +00:00
..
com	sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it	2015-03-02 08:36:39 +01:00
cpu	litescope: create example design derived from SoC that can be used on all targets	2015-02-28 22:19:24 +01:00
mem	litesata/kc705: use FMC pin names	2015-03-03 01:02:50 +00:00
others	move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future)	2015-02-28 11:51:51 +01:00
soc	cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)	2015-03-02 16:52:17 +01:00
tools	uart: use data instead of d on endpoint's layouts (coherency with others cores)	2015-03-01 16:56:48 +01:00
video	sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it	2015-03-02 08:36:39 +01:00
__init__.py	…