Florent Kermarrec b305b7828a sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it		2015-03-02 08:36:39 +01:00
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liteeth	liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen	2015-03-01 16:48:41 +01:00
liteusb	…
spi	…
uart	soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)	2015-03-01 18:25:47 +01:00
__init__.py	…