2015-06-27 20:10:45 -04:00
|
|
|
// This is free and unencumbered software released into the public domain.
|
2015-07-02 04:49:35 -04:00
|
|
|
//
|
2015-06-27 20:10:45 -04:00
|
|
|
// Anyone is free to copy, modify, publish, use, compile, sell, or
|
|
|
|
|
// distribute this software, either in source code form or as a compiled
|
|
|
|
|
// binary, for any purpose, commercial or non-commercial, and by any
|
|
|
|
|
// means.
|
|
|
|
|
|
2015-06-28 16:09:51 -04:00
|
|
|
#define ENABLE_QREGS
|
2015-06-27 16:31:24 -04:00
|
|
|
#define ENABLE_RVTST
|
|
|
|
|
#define ENABLE_SIEVE
|
|
|
|
|
#define ENABLE_MULTST
|
|
|
|
|
#define ENABLE_STATS
|
|
|
|
|
|
2015-06-28 16:09:51 -04:00
|
|
|
#ifndef ENABLE_QREGS
|
|
|
|
|
# undef ENABLE_RVTST
|
|
|
|
|
#endif
|
|
|
|
|
|
2016-01-21 05:58:38 -05:00
|
|
|
// Only save registers in IRQ wrapper that are to be saved by the caller in
|
|
|
|
|
// the RISC-V ABI, with the excpetion of the stack pointer. The IRQ handler
|
|
|
|
|
// will save the rest if necessary. I.e. skip x3, x4, x8, x9, and x18-x27.
|
|
|
|
|
#undef ENABLE_FASTIRQ
|
|
|
|
|
|
2015-06-27 20:10:45 -04:00
|
|
|
#include "custom_ops.S"
|
|
|
|
|
|
2015-06-06 08:01:37 -04:00
|
|
|
.section .text
|
2015-06-25 08:08:39 -04:00
|
|
|
.global irq
|
2015-06-06 08:01:37 -04:00
|
|
|
.global sieve
|
2015-06-26 17:14:38 -04:00
|
|
|
.global multest
|
|
|
|
|
.global hard_mul
|
|
|
|
|
.global hard_mulh
|
|
|
|
|
.global hard_mulhsu
|
|
|
|
|
.global hard_mulhu
|
2015-06-06 08:01:37 -04:00
|
|
|
.global stats
|
|
|
|
|
|
2015-06-25 08:08:39 -04:00
|
|
|
reset_vec:
|
2015-06-27 20:10:45 -04:00
|
|
|
// no more than 16 bytes here !
|
|
|
|
|
waitirq zero
|
|
|
|
|
maskirq zero, zero
|
2015-06-25 08:08:39 -04:00
|
|
|
j start
|
|
|
|
|
|
2015-06-27 20:10:45 -04:00
|
|
|
|
|
|
|
|
/* Interrupt handler
|
|
|
|
|
**********************************/
|
|
|
|
|
|
|
|
|
|
.balign 16
|
2015-06-25 08:08:39 -04:00
|
|
|
irq_vec:
|
|
|
|
|
/* save registers */
|
|
|
|
|
|
2015-06-28 16:09:51 -04:00
|
|
|
#ifdef ENABLE_QREGS
|
|
|
|
|
|
2015-06-27 20:10:45 -04:00
|
|
|
setq q2, x1
|
|
|
|
|
setq q3, x2
|
2015-06-25 08:08:39 -04:00
|
|
|
|
|
|
|
|
lui x1, %hi(irq_regs)
|
|
|
|
|
addi x1, x1, %lo(irq_regs)
|
|
|
|
|
|
2015-06-27 20:10:45 -04:00
|
|
|
getq x2, q0
|
2015-06-25 08:08:39 -04:00
|
|
|
sw x2, 0*4(x1)
|
|
|
|
|
|
2015-06-27 20:10:45 -04:00
|
|
|
getq x2, q2
|
2015-06-25 08:08:39 -04:00
|
|
|
sw x2, 1*4(x1)
|
|
|
|
|
|
2015-06-27 20:10:45 -04:00
|
|
|
getq x2, q3
|
2015-06-25 08:08:39 -04:00
|
|
|
sw x2, 2*4(x1)
|
|
|
|
|
|
2016-01-21 05:58:38 -05:00
|
|
|
#ifdef ENABLE_FASTIRQ
|
|
|
|
|
sw x5, 5*4(x1)
|
|
|
|
|
sw x6, 6*4(x1)
|
|
|
|
|
sw x7, 7*4(x1)
|
|
|
|
|
sw x10, 10*4(x1)
|
|
|
|
|
sw x11, 11*4(x1)
|
|
|
|
|
sw x12, 12*4(x1)
|
|
|
|
|
sw x13, 13*4(x1)
|
|
|
|
|
sw x14, 14*4(x1)
|
|
|
|
|
sw x15, 15*4(x1)
|
|
|
|
|
sw x16, 16*4(x1)
|
|
|
|
|
sw x17, 17*4(x1)
|
|
|
|
|
sw x28, 28*4(x1)
|
|
|
|
|
sw x29, 29*4(x1)
|
|
|
|
|
sw x30, 30*4(x1)
|
|
|
|
|
sw x31, 31*4(x1)
|
|
|
|
|
#else
|
2015-06-25 08:08:39 -04:00
|
|
|
sw x3, 3*4(x1)
|
|
|
|
|
sw x4, 4*4(x1)
|
|
|
|
|
sw x5, 5*4(x1)
|
|
|
|
|
sw x6, 6*4(x1)
|
|
|
|
|
sw x7, 7*4(x1)
|
|
|
|
|
sw x8, 8*4(x1)
|
|
|
|
|
sw x9, 9*4(x1)
|
|
|
|
|
sw x10, 10*4(x1)
|
|
|
|
|
sw x11, 11*4(x1)
|
|
|
|
|
sw x12, 12*4(x1)
|
|
|
|
|
sw x13, 13*4(x1)
|
|
|
|
|
sw x14, 14*4(x1)
|
|
|
|
|
sw x15, 15*4(x1)
|
|
|
|
|
sw x16, 16*4(x1)
|
|
|
|
|
sw x17, 17*4(x1)
|
|
|
|
|
sw x18, 18*4(x1)
|
|
|
|
|
sw x19, 19*4(x1)
|
|
|
|
|
sw x20, 20*4(x1)
|
|
|
|
|
sw x21, 21*4(x1)
|
|
|
|
|
sw x22, 22*4(x1)
|
|
|
|
|
sw x23, 23*4(x1)
|
|
|
|
|
sw x24, 24*4(x1)
|
|
|
|
|
sw x25, 25*4(x1)
|
|
|
|
|
sw x26, 26*4(x1)
|
|
|
|
|
sw x27, 27*4(x1)
|
|
|
|
|
sw x28, 28*4(x1)
|
|
|
|
|
sw x29, 29*4(x1)
|
|
|
|
|
sw x30, 30*4(x1)
|
|
|
|
|
sw x31, 31*4(x1)
|
2016-01-21 05:58:38 -05:00
|
|
|
#endif
|
2015-06-25 08:08:39 -04:00
|
|
|
|
2015-06-28 16:09:51 -04:00
|
|
|
#else // ENABLE_QREGS
|
|
|
|
|
|
2016-01-21 05:58:38 -05:00
|
|
|
#ifdef ENABLE_FASTIRQ
|
|
|
|
|
sw gp, 0*4+0x200(zero)
|
|
|
|
|
sw x1, 1*4+0x200(zero)
|
|
|
|
|
sw x2, 2*4+0x200(zero)
|
|
|
|
|
sw x5, 5*4+0x200(zero)
|
|
|
|
|
sw x6, 6*4+0x200(zero)
|
|
|
|
|
sw x7, 7*4+0x200(zero)
|
|
|
|
|
sw x10, 10*4+0x200(zero)
|
|
|
|
|
sw x11, 11*4+0x200(zero)
|
|
|
|
|
sw x12, 12*4+0x200(zero)
|
|
|
|
|
sw x13, 13*4+0x200(zero)
|
|
|
|
|
sw x14, 14*4+0x200(zero)
|
|
|
|
|
sw x15, 15*4+0x200(zero)
|
|
|
|
|
sw x16, 16*4+0x200(zero)
|
|
|
|
|
sw x17, 17*4+0x200(zero)
|
|
|
|
|
sw x28, 28*4+0x200(zero)
|
|
|
|
|
sw x29, 29*4+0x200(zero)
|
|
|
|
|
sw x30, 30*4+0x200(zero)
|
|
|
|
|
sw x31, 31*4+0x200(zero)
|
|
|
|
|
#else
|
2015-06-28 16:09:51 -04:00
|
|
|
sw gp, 0*4+0x200(zero)
|
|
|
|
|
sw x1, 1*4+0x200(zero)
|
|
|
|
|
sw x2, 2*4+0x200(zero)
|
|
|
|
|
sw x3, 3*4+0x200(zero)
|
|
|
|
|
sw x4, 4*4+0x200(zero)
|
|
|
|
|
sw x5, 5*4+0x200(zero)
|
|
|
|
|
sw x6, 6*4+0x200(zero)
|
|
|
|
|
sw x7, 7*4+0x200(zero)
|
|
|
|
|
sw x8, 8*4+0x200(zero)
|
|
|
|
|
sw x9, 9*4+0x200(zero)
|
|
|
|
|
sw x10, 10*4+0x200(zero)
|
|
|
|
|
sw x11, 11*4+0x200(zero)
|
|
|
|
|
sw x12, 12*4+0x200(zero)
|
|
|
|
|
sw x13, 13*4+0x200(zero)
|
|
|
|
|
sw x14, 14*4+0x200(zero)
|
|
|
|
|
sw x15, 15*4+0x200(zero)
|
|
|
|
|
sw x16, 16*4+0x200(zero)
|
|
|
|
|
sw x17, 17*4+0x200(zero)
|
|
|
|
|
sw x18, 18*4+0x200(zero)
|
|
|
|
|
sw x19, 19*4+0x200(zero)
|
|
|
|
|
sw x20, 20*4+0x200(zero)
|
|
|
|
|
sw x21, 21*4+0x200(zero)
|
|
|
|
|
sw x22, 22*4+0x200(zero)
|
|
|
|
|
sw x23, 23*4+0x200(zero)
|
|
|
|
|
sw x24, 24*4+0x200(zero)
|
|
|
|
|
sw x25, 25*4+0x200(zero)
|
|
|
|
|
sw x26, 26*4+0x200(zero)
|
|
|
|
|
sw x27, 27*4+0x200(zero)
|
|
|
|
|
sw x28, 28*4+0x200(zero)
|
|
|
|
|
sw x29, 29*4+0x200(zero)
|
|
|
|
|
sw x30, 30*4+0x200(zero)
|
|
|
|
|
sw x31, 31*4+0x200(zero)
|
2016-01-21 05:58:38 -05:00
|
|
|
#endif
|
2015-06-28 16:09:51 -04:00
|
|
|
|
|
|
|
|
#endif // ENABLE_QREGS
|
|
|
|
|
|
2015-06-27 20:10:45 -04:00
|
|
|
/* call interrupt handler C function */
|
2015-06-25 08:08:39 -04:00
|
|
|
|
2015-06-27 20:10:45 -04:00
|
|
|
lui sp, %hi(irq_stack)
|
|
|
|
|
addi sp, sp, %lo(irq_stack)
|
2015-06-25 08:08:39 -04:00
|
|
|
|
|
|
|
|
// arg0 = address of regs
|
|
|
|
|
lui a0, %hi(irq_regs)
|
|
|
|
|
addi a0, a0, %lo(irq_regs)
|
|
|
|
|
|
|
|
|
|
// arg1 = interrupt type
|
2015-06-28 16:09:51 -04:00
|
|
|
#ifdef ENABLE_QREGS
|
2015-06-28 14:52:52 -04:00
|
|
|
getq a1, q1
|
2015-06-28 16:09:51 -04:00
|
|
|
#else
|
|
|
|
|
addi a1, tp, 0
|
|
|
|
|
#endif
|
2015-06-25 08:08:39 -04:00
|
|
|
|
2015-06-27 20:10:45 -04:00
|
|
|
// call to C function
|
2015-06-25 08:08:39 -04:00
|
|
|
jal ra, irq
|
|
|
|
|
|
|
|
|
|
/* restore registers */
|
|
|
|
|
|
2015-06-28 16:09:51 -04:00
|
|
|
#ifdef ENABLE_QREGS
|
|
|
|
|
|
2015-06-28 14:52:52 -04:00
|
|
|
// new irq_regs address returned from C code in a0
|
|
|
|
|
addi x1, a0, 0
|
2015-06-25 08:08:39 -04:00
|
|
|
|
|
|
|
|
lw x2, 0*4(x1)
|
2015-06-27 20:10:45 -04:00
|
|
|
setq q0, x2
|
2015-06-25 08:08:39 -04:00
|
|
|
|
|
|
|
|
lw x2, 1*4(x1)
|
2015-06-27 20:10:45 -04:00
|
|
|
setq q1, x2
|
2015-06-25 08:08:39 -04:00
|
|
|
|
|
|
|
|
lw x2, 2*4(x1)
|
2015-06-27 20:10:45 -04:00
|
|
|
setq q2, x2
|
2015-06-25 08:08:39 -04:00
|
|
|
|
2016-01-21 05:58:38 -05:00
|
|
|
#ifdef ENABLE_FASTIRQ
|
|
|
|
|
lw x5, 5*4(x1)
|
|
|
|
|
lw x6, 6*4(x1)
|
|
|
|
|
lw x7, 7*4(x1)
|
|
|
|
|
lw x10, 10*4(x1)
|
|
|
|
|
lw x11, 11*4(x1)
|
|
|
|
|
lw x12, 12*4(x1)
|
|
|
|
|
lw x13, 13*4(x1)
|
|
|
|
|
lw x14, 14*4(x1)
|
|
|
|
|
lw x15, 15*4(x1)
|
|
|
|
|
lw x16, 16*4(x1)
|
|
|
|
|
lw x17, 17*4(x1)
|
|
|
|
|
lw x28, 28*4(x1)
|
|
|
|
|
lw x29, 29*4(x1)
|
|
|
|
|
lw x30, 30*4(x1)
|
|
|
|
|
lw x31, 31*4(x1)
|
|
|
|
|
#else
|
2015-06-25 08:08:39 -04:00
|
|
|
lw x3, 3*4(x1)
|
|
|
|
|
lw x4, 4*4(x1)
|
|
|
|
|
lw x5, 5*4(x1)
|
|
|
|
|
lw x6, 6*4(x1)
|
|
|
|
|
lw x7, 7*4(x1)
|
|
|
|
|
lw x8, 8*4(x1)
|
|
|
|
|
lw x9, 9*4(x1)
|
|
|
|
|
lw x10, 10*4(x1)
|
|
|
|
|
lw x11, 11*4(x1)
|
|
|
|
|
lw x12, 12*4(x1)
|
|
|
|
|
lw x13, 13*4(x1)
|
|
|
|
|
lw x14, 14*4(x1)
|
|
|
|
|
lw x15, 15*4(x1)
|
|
|
|
|
lw x16, 16*4(x1)
|
|
|
|
|
lw x17, 17*4(x1)
|
|
|
|
|
lw x18, 18*4(x1)
|
|
|
|
|
lw x19, 19*4(x1)
|
|
|
|
|
lw x20, 20*4(x1)
|
|
|
|
|
lw x21, 21*4(x1)
|
|
|
|
|
lw x22, 22*4(x1)
|
|
|
|
|
lw x23, 23*4(x1)
|
|
|
|
|
lw x24, 24*4(x1)
|
|
|
|
|
lw x25, 25*4(x1)
|
|
|
|
|
lw x26, 26*4(x1)
|
|
|
|
|
lw x27, 27*4(x1)
|
|
|
|
|
lw x28, 28*4(x1)
|
|
|
|
|
lw x29, 29*4(x1)
|
|
|
|
|
lw x30, 30*4(x1)
|
|
|
|
|
lw x31, 31*4(x1)
|
2016-01-21 05:58:38 -05:00
|
|
|
#endif
|
2015-06-25 08:08:39 -04:00
|
|
|
|
2015-06-27 20:10:45 -04:00
|
|
|
getq x1, q1
|
|
|
|
|
getq x2, q2
|
2015-06-25 08:08:39 -04:00
|
|
|
|
2015-06-28 16:09:51 -04:00
|
|
|
#else // ENABLE_QREGS
|
|
|
|
|
|
|
|
|
|
// new irq_regs address returned from C code in a0
|
|
|
|
|
addi a1, zero, 0x200
|
|
|
|
|
beq a0, a1, 1f
|
|
|
|
|
sbreak
|
|
|
|
|
1:
|
|
|
|
|
|
2016-01-21 05:58:38 -05:00
|
|
|
#ifdef ENABLE_FASTIRQ
|
|
|
|
|
lw gp, 0*4+0x200(zero)
|
|
|
|
|
lw x1, 1*4+0x200(zero)
|
|
|
|
|
lw x2, 2*4+0x200(zero)
|
|
|
|
|
lw x5, 5*4+0x200(zero)
|
|
|
|
|
lw x6, 6*4+0x200(zero)
|
|
|
|
|
lw x7, 7*4+0x200(zero)
|
|
|
|
|
lw x10, 10*4+0x200(zero)
|
|
|
|
|
lw x11, 11*4+0x200(zero)
|
|
|
|
|
lw x12, 12*4+0x200(zero)
|
|
|
|
|
lw x13, 13*4+0x200(zero)
|
|
|
|
|
lw x14, 14*4+0x200(zero)
|
|
|
|
|
lw x15, 15*4+0x200(zero)
|
|
|
|
|
lw x16, 16*4+0x200(zero)
|
|
|
|
|
lw x17, 17*4+0x200(zero)
|
|
|
|
|
lw x28, 28*4+0x200(zero)
|
|
|
|
|
lw x29, 29*4+0x200(zero)
|
|
|
|
|
lw x30, 30*4+0x200(zero)
|
|
|
|
|
lw x31, 31*4+0x200(zero)
|
|
|
|
|
#else
|
2015-06-28 16:09:51 -04:00
|
|
|
lw gp, 0*4+0x200(zero)
|
|
|
|
|
lw x1, 1*4+0x200(zero)
|
|
|
|
|
lw x2, 2*4+0x200(zero)
|
|
|
|
|
// do not restore x3 (gp)
|
|
|
|
|
lw x4, 4*4+0x200(zero)
|
|
|
|
|
lw x5, 5*4+0x200(zero)
|
|
|
|
|
lw x6, 6*4+0x200(zero)
|
|
|
|
|
lw x7, 7*4+0x200(zero)
|
|
|
|
|
lw x8, 8*4+0x200(zero)
|
|
|
|
|
lw x9, 9*4+0x200(zero)
|
|
|
|
|
lw x10, 10*4+0x200(zero)
|
|
|
|
|
lw x11, 11*4+0x200(zero)
|
|
|
|
|
lw x12, 12*4+0x200(zero)
|
|
|
|
|
lw x13, 13*4+0x200(zero)
|
|
|
|
|
lw x14, 14*4+0x200(zero)
|
|
|
|
|
lw x15, 15*4+0x200(zero)
|
|
|
|
|
lw x16, 16*4+0x200(zero)
|
|
|
|
|
lw x17, 17*4+0x200(zero)
|
|
|
|
|
lw x18, 18*4+0x200(zero)
|
|
|
|
|
lw x19, 19*4+0x200(zero)
|
|
|
|
|
lw x20, 20*4+0x200(zero)
|
|
|
|
|
lw x21, 21*4+0x200(zero)
|
|
|
|
|
lw x22, 22*4+0x200(zero)
|
|
|
|
|
lw x23, 23*4+0x200(zero)
|
|
|
|
|
lw x24, 24*4+0x200(zero)
|
|
|
|
|
lw x25, 25*4+0x200(zero)
|
|
|
|
|
lw x26, 26*4+0x200(zero)
|
|
|
|
|
lw x27, 27*4+0x200(zero)
|
|
|
|
|
lw x28, 28*4+0x200(zero)
|
|
|
|
|
lw x29, 29*4+0x200(zero)
|
|
|
|
|
lw x30, 30*4+0x200(zero)
|
|
|
|
|
lw x31, 31*4+0x200(zero)
|
2016-01-21 05:58:38 -05:00
|
|
|
#endif
|
2015-06-28 16:09:51 -04:00
|
|
|
|
|
|
|
|
#endif // ENABLE_QREGS
|
|
|
|
|
|
2015-06-27 20:10:45 -04:00
|
|
|
retirq
|
2015-06-25 08:08:39 -04:00
|
|
|
|
2015-06-28 16:09:51 -04:00
|
|
|
#ifndef ENABLE_QREGS
|
|
|
|
|
.balign 0x200
|
|
|
|
|
#endif
|
2015-06-25 08:08:39 -04:00
|
|
|
irq_regs:
|
2015-06-27 20:10:45 -04:00
|
|
|
// registers are saved to this memory region during interrupt handling
|
2015-06-25 08:08:39 -04:00
|
|
|
// the program counter is saved as register 0
|
|
|
|
|
.fill 32,4
|
|
|
|
|
|
2015-06-27 20:10:45 -04:00
|
|
|
// stack for the interrupt handler
|
2015-06-25 08:08:39 -04:00
|
|
|
.fill 128,4
|
2015-06-27 20:10:45 -04:00
|
|
|
irq_stack:
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Main program
|
|
|
|
|
**********************************/
|
2015-06-25 08:08:39 -04:00
|
|
|
|
2015-06-06 08:01:37 -04:00
|
|
|
start:
|
2015-06-27 20:10:45 -04:00
|
|
|
/* zero-initialize all registers */
|
|
|
|
|
|
2015-06-25 08:08:39 -04:00
|
|
|
addi x1, zero, 0
|
|
|
|
|
addi x2, zero, 0
|
|
|
|
|
addi x3, zero, 0
|
|
|
|
|
addi x4, zero, 0
|
|
|
|
|
addi x5, zero, 0
|
|
|
|
|
addi x6, zero, 0
|
|
|
|
|
addi x7, zero, 0
|
|
|
|
|
addi x8, zero, 0
|
|
|
|
|
addi x9, zero, 0
|
|
|
|
|
addi x10, zero, 0
|
|
|
|
|
addi x11, zero, 0
|
|
|
|
|
addi x12, zero, 0
|
|
|
|
|
addi x13, zero, 0
|
|
|
|
|
addi x14, zero, 0
|
|
|
|
|
addi x15, zero, 0
|
|
|
|
|
addi x16, zero, 0
|
|
|
|
|
addi x17, zero, 0
|
|
|
|
|
addi x18, zero, 0
|
|
|
|
|
addi x19, zero, 0
|
|
|
|
|
addi x20, zero, 0
|
|
|
|
|
addi x21, zero, 0
|
|
|
|
|
addi x22, zero, 0
|
|
|
|
|
addi x23, zero, 0
|
|
|
|
|
addi x24, zero, 0
|
|
|
|
|
addi x25, zero, 0
|
|
|
|
|
addi x26, zero, 0
|
|
|
|
|
addi x27, zero, 0
|
|
|
|
|
addi x28, zero, 0
|
|
|
|
|
addi x29, zero, 0
|
|
|
|
|
addi x30, zero, 0
|
|
|
|
|
addi x31, zero, 0
|
|
|
|
|
|
2015-06-27 20:10:45 -04:00
|
|
|
/* running tests from riscv-tests */
|
|
|
|
|
|
|
|
|
|
#ifdef ENABLE_RVTST
|
|
|
|
|
# define TEST(n) \
|
|
|
|
|
.global n; \
|
|
|
|
|
addi x1, zero, 1000; \
|
|
|
|
|
timer zero, x1; \
|
|
|
|
|
jal zero,n; \
|
|
|
|
|
.global n ## _ret; \
|
|
|
|
|
n ## _ret:
|
|
|
|
|
#else
|
|
|
|
|
# define TEST(n) \
|
|
|
|
|
.global n ## _ret; \
|
|
|
|
|
n ## _ret:
|
|
|
|
|
#endif
|
|
|
|
|
|
2015-06-06 08:01:37 -04:00
|
|
|
TEST(lui)
|
|
|
|
|
TEST(auipc)
|
|
|
|
|
TEST(j)
|
|
|
|
|
TEST(jal)
|
|
|
|
|
TEST(jalr)
|
|
|
|
|
|
|
|
|
|
TEST(beq)
|
|
|
|
|
TEST(bne)
|
|
|
|
|
TEST(blt)
|
|
|
|
|
TEST(bge)
|
|
|
|
|
TEST(bltu)
|
|
|
|
|
TEST(bgeu)
|
|
|
|
|
|
|
|
|
|
TEST(lb)
|
|
|
|
|
TEST(lh)
|
|
|
|
|
TEST(lw)
|
|
|
|
|
TEST(lbu)
|
|
|
|
|
TEST(lhu)
|
|
|
|
|
|
|
|
|
|
TEST(sb)
|
|
|
|
|
TEST(sh)
|
|
|
|
|
TEST(sw)
|
|
|
|
|
|
|
|
|
|
TEST(addi)
|
|
|
|
|
TEST(slti) // also tests sltiu
|
|
|
|
|
TEST(xori)
|
|
|
|
|
TEST(ori)
|
|
|
|
|
TEST(andi)
|
|
|
|
|
TEST(slli)
|
|
|
|
|
TEST(srli)
|
|
|
|
|
TEST(srai)
|
|
|
|
|
|
|
|
|
|
TEST(add)
|
|
|
|
|
TEST(sub)
|
|
|
|
|
TEST(sll)
|
|
|
|
|
TEST(slt) // what is with sltu ?
|
|
|
|
|
TEST(xor)
|
|
|
|
|
TEST(srl)
|
|
|
|
|
TEST(sra)
|
|
|
|
|
TEST(or)
|
|
|
|
|
TEST(and)
|
|
|
|
|
|
2015-06-27 16:18:24 -04:00
|
|
|
TEST(mulh)
|
|
|
|
|
TEST(mulhsu)
|
|
|
|
|
TEST(mulhu)
|
|
|
|
|
TEST(mul)
|
|
|
|
|
|
2016-04-10 10:54:35 -04:00
|
|
|
TEST(div)
|
|
|
|
|
TEST(divu)
|
|
|
|
|
TEST(rem)
|
|
|
|
|
TEST(remu)
|
|
|
|
|
|
2015-06-06 08:01:37 -04:00
|
|
|
TEST(simple)
|
|
|
|
|
|
|
|
|
|
/* set stack pointer */
|
|
|
|
|
lui sp,(64*1024)>>12
|
|
|
|
|
|
2015-06-28 14:52:52 -04:00
|
|
|
/* set gp and tp */
|
|
|
|
|
lui gp, %hi(0xdeadbeef)
|
|
|
|
|
addi gp, gp, %lo(0xdeadbeef)
|
|
|
|
|
addi tp, gp, 0
|
|
|
|
|
|
2015-06-27 16:31:24 -04:00
|
|
|
#ifdef ENABLE_SIEVE
|
|
|
|
|
/* call sieve C code */
|
2015-06-06 08:01:37 -04:00
|
|
|
jal ra,sieve
|
2015-06-27 16:31:24 -04:00
|
|
|
#endif
|
2015-06-06 08:01:37 -04:00
|
|
|
|
2015-06-27 16:31:24 -04:00
|
|
|
#ifdef ENABLE_MULTST
|
2015-06-28 08:56:26 -04:00
|
|
|
/* call multest C code */
|
2015-06-26 17:14:38 -04:00
|
|
|
jal ra,multest
|
2015-06-27 16:31:24 -04:00
|
|
|
#endif
|
2015-06-26 17:14:38 -04:00
|
|
|
|
2015-06-27 16:31:24 -04:00
|
|
|
#ifdef ENABLE_STATS
|
|
|
|
|
/* call stats C code */
|
2015-06-06 08:01:37 -04:00
|
|
|
jal ra,stats
|
2015-06-27 16:31:24 -04:00
|
|
|
#endif
|
2015-06-06 08:01:37 -04:00
|
|
|
|
|
|
|
|
/* print "DONE\n" */
|
|
|
|
|
lui a0,0x10000000>>12
|
|
|
|
|
addi a1,zero,'D'
|
|
|
|
|
addi a2,zero,'O'
|
|
|
|
|
addi a3,zero,'N'
|
|
|
|
|
addi a4,zero,'E'
|
|
|
|
|
addi a5,zero,'\n'
|
|
|
|
|
sw a1,0(a0)
|
|
|
|
|
sw a2,0(a0)
|
|
|
|
|
sw a3,0(a0)
|
|
|
|
|
sw a4,0(a0)
|
|
|
|
|
sw a5,0(a0)
|
|
|
|
|
|
|
|
|
|
/* break */
|
|
|
|
|
sbreak
|
|
|
|
|
|
2015-06-28 07:07:50 -04:00
|
|
|
|
|
|
|
|
/* Hard mul functions for multest.c
|
|
|
|
|
**********************************/
|
|
|
|
|
|
2015-06-26 17:14:38 -04:00
|
|
|
hard_mul:
|
|
|
|
|
mul a0, a0, a1
|
|
|
|
|
ret
|
|
|
|
|
|
|
|
|
|
hard_mulh:
|
|
|
|
|
mulh a0, a0, a1
|
|
|
|
|
ret
|
|
|
|
|
|
|
|
|
|
hard_mulhsu:
|
|
|
|
|
mulhsu a0, a0, a1
|
|
|
|
|
ret
|
|
|
|
|
|
|
|
|
|
hard_mulhu:
|
|
|
|
|
mulhu a0, a0, a1
|
|
|
|
|
ret
|
|
|
|
|
|
