picorv32/scripts/icestorm/Makefile

105 lines
2.4 KiB
Makefile
Raw Normal View History

2015-10-08 05:58:59 -04:00
TOOLCHAIN_PREFIX = riscv32-unknown-elf-
2015-07-19 10:09:19 -04:00
ICE40_SIM_CELLS=$(shell yosys-config --datdir/ice40/cells_sim.v)
# set to 4 for simulation
FIRMWARE_COUNTER_BITS=18
2015-07-19 10:09:19 -04:00
all: example.bin
## -------------------
## firmware generation
2015-07-19 10:09:19 -04:00
firmware.elf: firmware.S firmware.c firmware.lds
$(TOOLCHAIN_PREFIX)gcc \
-DSHIFT_COUNTER_BITS=$(FIRMWARE_COUNTER_BITS) \
-march=rv32i -Os -ffreestanding -nostdlib \
-o $@ firmware.S firmware.c \
--std=gnu99 -Wl,-Bstatic,-T,firmware.lds,-Map,firmware.map,--strip-debug
chmod -x $@
2015-07-19 10:09:19 -04:00
firmware.bin: firmware.elf
$(TOOLCHAIN_PREFIX)objcopy -O binary $< $@
chmod -x $@
2015-07-19 10:09:19 -04:00
firmware.hex: firmware.bin
python3 ../../firmware/makehex.py $< 128 > $@
2015-07-19 10:09:19 -04:00
## ------------------------------
## main flow: synth/p&r/bitstream
synth.json: example.v ../../picorv32.v firmware.hex
yosys -v3 -l synth.log -p 'synth_ice40 -top top -json $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
2015-07-19 10:09:19 -04:00
example.asc: synth.json example.pcf
nextpnr-ice40 --hx8k --package ct256 --json $< --pcf example.pcf --asc $@
2015-07-19 10:09:19 -04:00
2016-07-14 03:07:52 -04:00
example.bin: example.asc
icepack $< $@
2015-07-19 10:09:19 -04:00
## -----------------
## icarus simulation
example_tb.vvp: example.v example_tb.v ../../picorv32.v firmware.hex
iverilog -o $@ -s testbench $(filter %.v, $^)
chmod -x $@
2015-07-19 10:09:19 -04:00
example_sim: example_tb.vvp
vvp -N $<
2015-07-21 11:43:33 -04:00
example_sim_vcd: example_tb.vvp
vvp -N $< +vcd
2015-07-21 11:43:33 -04:00
## ---------------------
## post-synth simulation
synth_tb.vvp: example_tb.v synth.json
iverilog -o $@ -s testbench synth.v example_tb.v $(ICE40_SIM_CELLS)
chmod -x $@
2015-07-21 11:43:33 -04:00
synth_sim: synth_tb.vvp
vvp -N $<
2015-07-21 11:43:33 -04:00
synth_sim_vcd: synth_tb.vvp
vvp -N $< +vcd
2015-07-21 11:43:33 -04:00
## ---------------------
## post-route simulation
route.v: example.asc example.pcf
icebox_vlog -L -n top -sp example.pcf $< > $@
2015-07-21 11:43:33 -04:00
route_tb.vvp: route.v example_tb.v
iverilog -o $@ -s testbench $^ $(ICE40_SIM_CELLS)
chmod -x $@
2015-07-21 11:43:33 -04:00
route_sim: route_tb.vvp
vvp -N $<
2015-07-21 11:43:33 -04:00
route_sim_vcd: route_tb.vvp
vvp -N $< +vcd
2015-07-19 10:09:19 -04:00
## ---------------------
## miscellaneous targets
prog_sram: example.bin
iceprog -S $<
2015-07-19 10:09:19 -04:00
timing: example.asc example.pcf
icetime -c 62 -tmd hx8k -P ct256 -p example.pcf -t $<
view: example.vcd
gtkwave $< example.gtkw
2015-07-21 11:43:33 -04:00
## ------
## el fin
2015-07-19 10:09:19 -04:00
clean:
rm -f firmware.elf firmware.map firmware.bin firmware.hex
rm -f synth.log synth.v synth.json route.v example.asc example.bin
rm -f example_tb.vvp synth_tb.vvp route_tb.vvp example.vcd
2015-07-19 10:09:19 -04:00
2015-07-21 11:43:33 -04:00
.PHONY: all prog_sram view clean
.PHONY: example_sim synth_sim route_sim timing
2015-07-21 11:43:33 -04:00
.PHONY: example_sim_vcd synth_sim_vcd route_sim_vcd