picorv32/scripts/yosys/synth_sim.ys

# yosys synthesis script for post-synthesis simulation (make test_synth)

read_verilog picorv32.v
chparam -set COMPRESSED_ISA 1 -set ENABLE_MUL 1 -set ENABLE_DIV 1 \
        -set ENABLE_IRQ 1 -set ENABLE_TRACE 1 picorv32_axi
hierarchy -top picorv32_axi
synth
write_verilog synth.v
Added "make test_synth" 2015-06-29 19:46:25 -04:00			`# yosys synthesis script for post-synthesis simulation (make test_synth)`

			`read_verilog picorv32.v`
Fixed "make test_synth" 2016-12-15 06:48:57 -05:00			`chparam -set COMPRESSED_ISA 1 -set ENABLE_MUL 1 -set ENABLE_DIV 1 \`
			`-set ENABLE_IRQ 1 -set ENABLE_TRACE 1 picorv32_axi`
Added "make test_synth" 2015-06-29 19:46:25 -04:00			`hierarchy -top picorv32_axi`
			`synth`
			`write_verilog synth.v`