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Fixed PCPI instr prefetching

This commit is contained in:
Clifford Wolf 2015-06-28 14:51:53 +02:00
parent 094dc690bb
commit b076d72806
2 changed files with 5 additions and 5 deletions
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7
README.md
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@ -195,7 +195,7 @@ CPI numbers for a core built without ENABLE_REGS_DUALPORT.
| shift operations | 4-14 | 4-15 |
When `ENABLE_MUL` is activated, then a `MUL` instruction will execute
in 42 cycles and a `MULH[SU|U]` instruction will execute in 74 cycles.
in 40 cycles and a `MULH[SU|U]` instruction will execute in 72 cycles.
Dhrystone benchmark results: 0.309 DMIPS/MHz (544 Dhrystones/Second/MHz)
@ -405,12 +405,13 @@ enabled PCPI, IRQ and MUL features.
| PicoRV32 "regular" | 996 | 48 |
| PicoRV32 "large" | 1814 | 88 |
*Note: Most of the size reduction in the "small" core comes from eliminating
the counter instructions, not from reducing the size of the register file.*
Todos:
------
- Optional FENCE support
- Optional write-through cache
- Optional support for compressed ISA
- Improved documentation and examples

3
picorv32.v
View File

@ -164,8 +164,7 @@ module picorv32 #(
reg mem_do_wdata;
wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
wire mem_done = mem_ready && ((mem_state[0] && (mem_do_rinst || mem_do_rdata)) || mem_state == 2);
wire mem_done = (mem_ready && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst);
assign mem_la_write = resetn && !mem_state && mem_do_wdata;
assign mem_la_read = resetn && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata);