mirror of https://github.com/YosysHQ/picorv32.git
Improve and cleanup picosoc firmware
This commit is contained in:
parent
78f2f5efd2
commit
febb4b1318
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@ -3,7 +3,7 @@
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/spiflash_tb.vcd
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/spiflash_tb.vcd
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/spiflash_tb.vvp
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/spiflash_tb.vvp
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/firmware.elf
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/firmware.elf
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/firmware_vma.elf
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/firmware_up.elf
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/firmware.hex
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/firmware.hex
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/firmware.bin
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/firmware.bin
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/hx8kdemo.asc
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/hx8kdemo.asc
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@ -46,14 +46,14 @@ hx8kdemo.bin: hx8kdemo.asc
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# ---- Example Firmware ----
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# ---- Example Firmware ----
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firmware.elf: firmware.s
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firmware.elf: sections.lds firmware.S
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riscv32-unknown-elf-gcc -c -o firmware.elf firmware.s
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riscv32-unknown-elf-gcc -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf firmware.S
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firmware_vma.elf: firmware.elf
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firmware_up.elf: firmware.elf
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riscv32-unknown-elf-objcopy --change-section-vma .text=0x00100000 firmware.elf firmware_vma.elf
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riscv32-unknown-elf-objcopy --change-addresses 0x100000 firmware.elf firmware_up.elf
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firmware.hex: firmware_vma.elf
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firmware.hex: firmware_up.elf
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riscv32-unknown-elf-objcopy -O verilog firmware_vma.elf firmware.hex
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riscv32-unknown-elf-objcopy -O verilog firmware_up.elf firmware.hex
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firmware.bin: firmware.elf
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firmware.bin: firmware.elf
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riscv32-unknown-elf-objcopy -O binary firmware.elf firmware.bin
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riscv32-unknown-elf-objcopy -O binary firmware.elf firmware.bin
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@ -62,7 +62,7 @@ firmware.bin: firmware.elf
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clean:
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clean:
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rm -f testbench.vvp testbench.vcd spiflash_tb.vvp spiflash_tb.vcd
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rm -f testbench.vvp testbench.vcd spiflash_tb.vvp spiflash_tb.vcd
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rm -f firmware.elf firmware_vma.elf firmware.hex firmware.bin
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rm -f firmware.elf firmware_up.elf firmware.hex firmware.bin
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rm -f hx8kdemo.blif hx8kdemo.log hx8kdemo.asc hx8kdemo.rpt hx8kdemo.bin
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rm -f hx8kdemo.blif hx8kdemo.log hx8kdemo.asc hx8kdemo.rpt hx8kdemo.bin
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rm -f hx8kdemo_syn.v hx8kdemo_syn_tb.vvp hx8kdemo_tb.vvp
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rm -f hx8kdemo_syn.v hx8kdemo_syn_tb.vvp hx8kdemo_tb.vvp
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@ -1,5 +1,5 @@
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# write RAM code (a sequence of nops followed by ret)
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// write RAM code (a sequence of nops followed by ret)
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li x5,0x00000013 # nop
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li x5,0x00000013 // nop
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sw x5,4(x0)
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sw x5,4(x0)
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sw x5,8(x0)
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sw x5,8(x0)
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sw x5,12(x0)
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sw x5,12(x0)
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@ -48,38 +48,45 @@ sw x5,180(x0)
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sw x5,184(x0)
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sw x5,184(x0)
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sw x5,188(x0)
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sw x5,188(x0)
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sw x5,192(x0)
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sw x5,192(x0)
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li x5,0x00008067 # ret
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li x5,0x00008067 // ret
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sw x5,196(x0)
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sw x5,196(x0)
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# setup gpio address in x5
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#if 0
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// switch spimemio to continous qspi ddr mode
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li x5,0x02000000
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li x6,0x80000071
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sw x6,0(x5)
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#endif
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// setup gpio address in x5
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li x5,0x03000000
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li x5,0x03000000
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sw x0,0(x5)
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sw x0,0(x5)
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# initial entry point into RAM code
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// initial entry point into RAM code
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li x3,4
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li x3,4
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# initialize RAM counter
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// initialize RAM counter
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sw x0,0(x0)
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sw x0,0(x0)
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# start of loop. remember this address
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// start of loop. remember this address
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auipc x4,0
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auipc x4,0
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# execute RAM code, come back here
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// execute RAM code, come back here
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jalr x3
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jalr x3
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# load counter and increment
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// load counter and increment
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lw x6,0(x0)
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lw x6,0(x0)
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addi x6,x6,1
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addi x6,x6,1
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# store counter and update gpios
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// store counter and update gpios
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sw x6,0(x5)
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sw x6,0(x5)
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sw x6,0(x0)
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sw x6,0(x0)
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# calculate new entry point into RAM code
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// calculate new entry point into RAM code
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slli x3,x6,2
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slli x3,x6,2
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andi x3,x3,127
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andi x3,x3,127
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addi x3,x3,32
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addi x3,x3,32
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# execute RAM code, come back to start of loop
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// execute RAM code, come back to start of loop
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mv x1,x4
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mv x1,x4
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jr x3
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jr x3
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@ -0,0 +1,8 @@
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SECTIONS {
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.memory : {
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. = 0x000000;
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start*(.text);
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*(.text);
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*(*);
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}
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}
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@ -24,6 +24,10 @@ module testbench;
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always #5 clk = (clk === 1'b0);
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always #5 clk = (clk === 1'b0);
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reg resetn = 0;
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reg resetn = 0;
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integer cycles = 0;
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always @(posedge clk)
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cycles <= cycles + 1;
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initial begin
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initial begin
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$dumpfile("testbench.vcd");
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$dumpfile("testbench.vcd");
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@ -92,6 +96,7 @@ module testbench;
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$write("<GPIO:%02x>", gpio[7:0]);
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$write("<GPIO:%02x>", gpio[7:0]);
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if (gpio == 63) begin
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if (gpio == 63) begin
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$display("[OK]");
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$display("[OK]");
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$display("Finished after %0d cycles.", cycles);
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$finish;
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$finish;
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end
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end
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if (gpio % 8 == 7) begin
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if (gpio % 8 == 7) begin
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