2023-06-15 12:24:35 -04:00
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/* Copyright 2023 (C) Peter McGoron
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* This file is a part of Upsilon, a free and open source software project.
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* For license terms, refer to the files in `doc/copying` in the Upsilon
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* source distribution.
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*/
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2022-10-17 00:44:30 -04:00
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module sign_extend #(
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parameter WID1 = 18,
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parameter WID2 = 24
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) (
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2022-11-11 21:57:58 -05:00
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input [WID1-1:0] b1,
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output [WID2-1:0] b2
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2022-10-17 00:44:30 -04:00
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);
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assign b2[WID1-1:0] = b1;
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/* Assign the high bits of b2 to be the extension of the
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* highest bit of b1. If the MSB of b1 is 1 (i.e. b1 is
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* negative), then all high bits of b2 must be negative.
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* If the MSB of b1 is 0, then the high bits of b2 must
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* be zero.
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*/
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assign b2[WID2-1:WID1] = {(WID2-WID1){b1[WID1-1]}};
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endmodule
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