upsilon/gateware/Makefile

# Copyright 2023 (C) Peter McGoron
#
# This file is a part of Upsilon, a free and open source software project.
# For license terms, refer to the files in `doc/copying` in the Upsilon
# source distribution.
#
.PHONY: cpu clean rtl_codegen

DEVICETREE_GEN_DIR=.

all: rtl_codegen build/digilent_arty/digilent_arty.bit arty.dtb# mmio.py

rtl_codegen:
	cd rtl && make

csr.json build/digilent_arty/digilent_arty.bit: soc.py
	python3 soc.py

clean:
	rm -rf build csr.json arty.dts arty.dtb mmio.py
	cd rtl && make clean
test:
	cd rtl && make test

arty.dts: csr.json
	litex_json2dts_linux csr.json > arty.dts

arty.dtb: arty.dts
	dtc -O dtb -o arty.dtb arty.dts

#mmio.py: csr2mp.py csr.json
#	python3 csr2mp.py csr.json > mmio.py
make lawyers happy 2023-06-15 12:24:35 -04:00			`# Copyright 2023 (C) Peter McGoron`
			`#`
			`# This file is a part of Upsilon, a free and open source software project.`
			# For license terms, refer to the files in `doc/copying` in the Upsilon
			`# source distribution.`
			`#`
add missing .PHONY 2023-04-06 19:28:12 -04:00			`.PHONY: cpu clean rtl_codegen`
add devicetree generation 2022-07-12 15:22:14 -04:00
			`DEVICETREE_GEN_DIR=.`
Makefiles depend on generated files 2022-07-13 14:11:56 -04:00
Correctly finalize picorv32 module I think LiteX's SoCIORegions are reserved regions. Non-cached regions are then placed inside these reserved regions. Each module also has a "do_finalize" method that runs at code generation. 2024-02-04 09:47:39 -05:00			`all: rtl_codegen build/digilent_arty/digilent_arty.bit arty.dtb# mmio.py`
soc.py: fix syntax errors 2023-03-15 03:04:27 -04:00
codegen 2023-03-15 14:57:08 -04:00			`rtl_codegen:`
			`cd rtl && make`
Added makefile formatting 2023-08-23 22:09:34 -04:00
more work on linux upsilon 2023-05-30 16:01:32 -04:00			`csr.json build/digilent_arty/digilent_arty.bit: soc.py`
use add_constant() to modify network settings in SoC 2024-01-18 10:41:51 -05:00			`python3 soc.py`
Added makefile formatting 2023-08-23 22:09:34 -04:00
add makefile; condense LiteX CSRs 2022-07-12 13:29:26 -04:00			`clean:`
add ssh key 2023-06-22 15:59:06 -04:00			`rm -rf build csr.json arty.dts arty.dtb mmio.py`
update boothmul properly; add clean to make; hardware notes 2023-05-11 14:36:49 -04:00			`cd rtl && make clean`
change constants, bring back automated control loop tests, validate 2023-06-12 15:46:12 -04:00			`test:`
			`cd rtl && make test`
more work on linux upsilon 2023-05-30 16:01:32 -04:00
			`arty.dts: csr.json`
firmware/Makefile: update 2023-05-30 16:50:30 -04:00			`litex_json2dts_linux csr.json > arty.dts`
Added makefile formatting 2023-08-23 22:09:34 -04:00
more work on linux upsilon 2023-05-30 16:01:32 -04:00			`arty.dtb: arty.dts`
			`dtc -O dtb -o arty.dtb arty.dts`
add generate_csr_locations 2022-07-12 15:36:50 -04:00
Minor SPI fixes and Interconnect fix The previous code did not properly assign all values on all cases, and did not properly assign values (master interfaces, which are poorly named because they are the interfaces to the master, connect to the slave lines directly in the interconnect) 2024-02-02 19:33:52 -05:00			`#mmio.py: csr2mp.py csr.json`
			`# python3 csr2mp.py csr.json > mmio.py`