upsilon/firmware/rtl/control_loop/control_loop_sim_top.v

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`include "control_loop_cmds.vh"
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module control_loop_sim_top #(
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parameter ADC_WID = 18,
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parameter ADC_WID_SIZ = 5,
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parameter ADC_POLARITY = 1,
parameter ADC_PHASE = 0,
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parameter DAC_POLARITY = 0,
parameter DAC_PHASE = 1,
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parameter DAC_DATA_WID = 20,
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parameter DAC_WID = 24,
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parameter DAC_WID_SIZ = 5,
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parameter CONSTS_WHOLE = 21,
parameter CONSTS_FRAC = 43,
`define CONSTS_WID (CONSTS_WHOLE + CONSTS_FRAC)
parameter CONSTS_SIZ = 7,
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parameter DELAY_WID = 16
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)(
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input clk,
output in_loop,
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output [DAC_DATA_WID-1:0] curset,
output dac_err,
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input [ADC_WID-1:0] measured_value,
output request,
input fulfilled,
output adc_err,
input [`CONSTS_WID-1:0] word_into_loop,
output [`CONSTS_WID-1:0] word_outof_loop,
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input start_cmd,
output finish_cmd,
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input [`CONTROL_LOOP_CMD_WIDTH-1:0] cmd
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);
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/* Emulate a control loop environment with simulator controlled
SPI interfaces.
*/
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wire adc_miso;
wire adc_sck;
wire adc_ss_L;
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/* ADC */
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adc_sim #(
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.WID(ADC_WID),
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.WID_LEN(5),
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.POLARITY(ADC_POLARITY),
.PHASE(ADC_PHASE)
) adc (
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.clk(clk),
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.indat(measured_value),
.request(request),
.fulfilled(fulfilled),
.err(adc_err),
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.miso(adc_miso),
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.sck(adc_sck),
.ss_L(adc_ss_L)
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);
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wire dac_miso;
wire dac_mosi;
wire dac_ss_L;
wire dac_sck;
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/* DAC */
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dac_sim #(
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.WID(DAC_WID),
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.DATA_WID(DAC_DATA_WID),
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.WID_LEN(5),
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.POLARITY(DAC_POLARITY),
.PHASE(DAC_PHASE)
) dac (
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.clk(clk),
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.curset(curset),
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.mosi(dac_mosi),
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.miso(dac_miso),
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.sck(dac_sck),
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.ss_L(dac_ss_L),
.err(dac_err)
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);
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control_loop #(
.ADC_WID(ADC_WID),
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.ADC_WID_SIZ(ADC_WID_SIZ),
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.ADC_POLARITY(ADC_POLARITY),
.ADC_PHASE(ADC_PHASE),
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/* Keeping cycle half wait and conv wait the same
* since it doesn't matter for this simulation */
.CONSTS_WHOLE(CONSTS_WHOLE),
.CONSTS_FRAC(CONSTS_FRAC),
.CONSTS_SIZ(CONSTS_SIZ),
.DELAY_WID(DELAY_WID),
.DAC_WID(DAC_WID),
.DAC_WID_SIZ(DAC_WID_SIZ),
.DAC_DATA_WID(DAC_DATA_WID),
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.DAC_POLARITY(DAC_POLARITY),
.DAC_PHASE(DAC_PHASE)
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) cloop (
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.clk(clk),
.in_loop(in_loop),
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.dac_mosi(dac_mosi),
.dac_miso(dac_miso),
.dac_ss_L(dac_ss_L),
.dac_sck(dac_sck),
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.adc_miso(adc_miso),
.adc_conv_L(adc_ss_L),
.adc_sck(adc_sck),
.word_in(word_into_loop),
.word_out(word_outof_loop),
.start_cmd(start_cmd),
.finish_cmd(finish_cmd),
.cmd(cmd)
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);
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`ifdef VERILATOR
initial begin
$dumpfile("control_loop.fst");
$dumpvars;
end
`endif
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endmodule
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`undefineall