 Peter McGoron
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15b8fcbe7e
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reset pins and test clock
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2023-05-10 14:35:57 -04:00 |
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Peter McGoron
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40fd1ab6fe
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add debug clock
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2023-04-20 15:20:42 -04:00 |
|
Peter McGoron
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ab4c23fa14
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fix compile errors
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2023-04-18 15:47:57 -04:00 |
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Peter McGoron
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be4ed8afcf
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soc.py: fix compile errors
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2023-04-13 12:20:19 -04:00 |
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Peter McGoron
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e6c57ffa63
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soc.py: cleanup CSR generation
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2023-04-08 17:31:12 +00:00 |
|
Peter McGoron
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92a140d736
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generate_csr_locations: documentation
|
2023-04-08 16:47:59 +00:00 |
|
Peter McGoron
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a57b4ca91b
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generate_csr_locations.py: static const
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2023-04-08 16:45:48 +00:00 |
|
Peter McGoron
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5ff3ff675e
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COPYING: add A7-constraints.xdc
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2023-04-08 16:40:16 +00:00 |
|
Peter McGoron
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04b439a857
|
soc.py: documentation
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2023-04-08 16:38:24 +00:00 |
|
Peter McGoron
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27ada0d708
|
first pass at making correct memory accesses
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2023-04-08 16:05:52 +00:00 |
|
Peter McGoron
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9ff5576623
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add missing .PHONY
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2023-04-06 19:28:12 -04:00 |
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Peter McGoron
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79b71c7b0c
|
manual
|
2023-04-06 19:14:01 -04:00 |
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Peter McGoron
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e19a626945
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dac, adc switch and documentation
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2023-04-04 15:10:32 -04:00 |
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Peter McGoron
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b7ca97695a
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make software build system cleaner
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2023-04-04 12:24:58 -04:00 |
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Peter McGoron
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551f535513
|
compile
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2023-04-04 12:04:06 -04:00 |
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Peter McGoron
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0f86a60510
|
compile verilog
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2023-04-03 15:29:20 -04:00 |
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Peter McGoron
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eceb844e87
|
kernel
|
2023-04-03 04:39:26 +00:00 |
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Peter McGoron
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a26df53af5
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add wf_running to generate_csr_locations.py
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2023-04-03 03:13:54 +00:00 |
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Peter McGoron
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11f7cfd388
|
refactor soc.py base.v interface
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2023-04-02 21:35:51 +00:00 |
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Peter McGoron
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69f16264dd
|
add assertions
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2023-04-02 21:25:19 +00:00 |
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Peter McGoron
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66ea3ca0ea
|
waveform.v
fix potential hang in waveform.v
|
2023-04-02 21:20:26 +00:00 |
|
Peter McGoron
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a7da03f4b9
|
fix generate_csr_locations.py
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2023-03-20 15:07:52 -04:00 |
|
Peter McGoron
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908be977f5
|
merge
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2023-03-20 17:59:37 +00:00 |
|
Peter McGoron
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f90348aff9
|
arty.xdc for synth test
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2023-03-20 13:58:35 -04:00 |
|
Peter McGoron
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0259523d20
|
add yosys synth test for control loop
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2023-03-20 13:57:42 -04:00 |
|
Peter McGoron
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93c92b9f55
|
add test scripts for synthesizing ram fifo
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2023-03-20 13:57:15 -04:00 |
|
Peter McGoron
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368bbb6e2b
|
update generate_csr_locations
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2023-03-16 18:53:37 +00:00 |
|
Peter McGoron
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50ef091578
|
move preprocessed generation to common makefile
|
2023-03-16 16:32:03 +00:00 |
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Peter McGoron
|
55fc252382
|
pass yosys
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2023-03-15 17:08:55 -04:00 |
|
Peter McGoron
|
fbbd41c95e
|
codegen
|
2023-03-15 14:57:22 -04:00 |
|
Peter McGoron
|
ca8078f9d6
|
quick hack: pre-prepreprocess verilog files
|
2023-03-15 18:47:20 +00:00 |
|
Peter McGoron
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411c0c52c1
|
add control_loop_cmds header generators
|
2023-03-15 18:30:30 +00:00 |
|
Peter McGoron
|
953e42b80c
|
change control_loop to m4 scripts, add common makefile
|
2023-03-15 18:30:08 +00:00 |
|
Peter McGoron
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7af907ffb4
|
soc.py: fix syntax errors
|
2023-03-15 03:04:27 -04:00 |
|
Peter McGoron
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fefa6409cf
|
soc.py: add missing waveform pins
|
2023-03-15 06:30:59 +00:00 |
|
Peter McGoron
|
0f40b2cd95
|
base: add new waveform pins
|
2023-03-15 06:29:19 +00:00 |
|
Peter McGoron
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4142a0a1b4
|
simulate waveform.v
|
2023-03-15 06:24:28 +00:00 |
|
Peter McGoron
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c8f2cf1f7a
|
spi_switch: fix dangling else
|
2023-03-14 15:43:34 +00:00 |
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Peter McGoron
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90a49b6091
|
test and simulate spi_switch
|
2023-03-14 15:42:41 +00:00 |
|
Peter McGoron
|
36e5b964d5
|
lint base.v
|
2023-03-14 04:06:42 +00:00 |
|
Peter McGoron
|
d198273155
|
add base.m4
|
2023-03-14 01:40:17 +00:00 |
|
Peter McGoron
|
eadf374cd0
|
lint waveform.v
|
2023-03-10 22:59:26 +00:00 |
|
Peter McGoron
|
295eb8fad8
|
add base.v
|
2023-03-09 04:17:41 +00:00 |
|
Peter McGoron
|
89938a2ff6
|
move autoapproach to possibly useful waveform module: not yet tested
|
2023-03-03 18:30:00 +00:00 |
|
Peter McGoron
|
05f8878751
|
add submodules and switch
|
2023-03-03 08:06:50 +00:00 |
|
Peter McGoron
|
3a4224ff5b
|
merge
|
2023-02-25 21:17:18 +00:00 |
|
Peter McGoron
|
92091d0982
|
stuff
|
2023-02-25 21:17:04 +00:00 |
Shell-ac
|
556db1f361
|
Add files via upload
Verilog signal propagation testbench for the intsat module
|
2023-01-30 14:09:49 -05:00 |
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Peter McGoron
|
f88e0ef15c
|
Merge branch 'master' of ssh://github.com/phm19a/upsilon
|
2023-01-30 13:54:58 +00:00 |
|
Peter McGoron
|
b3a79f41ec
|
refactoring: move dma simulation to verilog
|
2023-01-30 13:54:17 +00:00 |