 Peter McGoron
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a1ff0b77c3
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licensing
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2023-05-29 13:56:11 -04:00 |
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Peter McGoron
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5178594215
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proper CSR location generation
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2023-05-16 15:02:05 -04:00 |
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Peter McGoron
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d0ec4cca9e
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convert differential outputs to single ended outputs
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2023-05-11 16:47:24 -04:00 |
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Peter McGoron
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0a9125355f
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disable test clock by default
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2023-05-11 15:31:52 -04:00 |
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Peter McGoron
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e1d09495da
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update boothmul properly; add clean to make; hardware notes
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2023-05-11 14:37:32 -04:00 |
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Peter McGoron
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f0624bf664
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adc debugging
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2023-05-11 11:43:30 -04:00 |
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Peter McGoron
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15b8fcbe7e
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reset pins and test clock
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2023-05-10 14:35:57 -04:00 |
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Peter McGoron
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40fd1ab6fe
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add debug clock
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2023-04-20 15:20:42 -04:00 |
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Peter McGoron
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ab4c23fa14
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fix compile errors
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2023-04-18 15:47:57 -04:00 |
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Peter McGoron
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be4ed8afcf
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soc.py: fix compile errors
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2023-04-13 12:20:19 -04:00 |
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Peter McGoron
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e6c57ffa63
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soc.py: cleanup CSR generation
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2023-04-08 17:31:12 +00:00 |
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Peter McGoron
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92a140d736
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generate_csr_locations: documentation
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2023-04-08 16:47:59 +00:00 |
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Peter McGoron
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a57b4ca91b
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generate_csr_locations.py: static const
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2023-04-08 16:45:48 +00:00 |
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Peter McGoron
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5ff3ff675e
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COPYING: add A7-constraints.xdc
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2023-04-08 16:40:16 +00:00 |
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Peter McGoron
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04b439a857
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soc.py: documentation
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2023-04-08 16:38:24 +00:00 |
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Peter McGoron
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27ada0d708
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first pass at making correct memory accesses
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2023-04-08 16:05:52 +00:00 |
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Peter McGoron
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9ff5576623
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add missing .PHONY
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2023-04-06 19:28:12 -04:00 |
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Peter McGoron
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79b71c7b0c
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manual
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2023-04-06 19:14:01 -04:00 |
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Peter McGoron
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e19a626945
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dac, adc switch and documentation
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2023-04-04 15:10:32 -04:00 |
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Peter McGoron
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b7ca97695a
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make software build system cleaner
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2023-04-04 12:24:58 -04:00 |
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Peter McGoron
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551f535513
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compile
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2023-04-04 12:04:06 -04:00 |
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Peter McGoron
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0f86a60510
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compile verilog
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2023-04-03 15:29:20 -04:00 |
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Peter McGoron
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eceb844e87
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kernel
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2023-04-03 04:39:26 +00:00 |
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Peter McGoron
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a26df53af5
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add wf_running to generate_csr_locations.py
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2023-04-03 03:13:54 +00:00 |
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Peter McGoron
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11f7cfd388
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refactor soc.py base.v interface
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2023-04-02 21:35:51 +00:00 |
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Peter McGoron
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69f16264dd
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add assertions
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2023-04-02 21:25:19 +00:00 |
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Peter McGoron
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66ea3ca0ea
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waveform.v
fix potential hang in waveform.v
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2023-04-02 21:20:26 +00:00 |
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Peter McGoron
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a7da03f4b9
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fix generate_csr_locations.py
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2023-03-20 15:07:52 -04:00 |
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Peter McGoron
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908be977f5
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merge
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2023-03-20 17:59:37 +00:00 |
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Peter McGoron
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f90348aff9
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arty.xdc for synth test
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2023-03-20 13:58:35 -04:00 |
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Peter McGoron
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0259523d20
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add yosys synth test for control loop
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2023-03-20 13:57:42 -04:00 |
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Peter McGoron
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93c92b9f55
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add test scripts for synthesizing ram fifo
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2023-03-20 13:57:15 -04:00 |
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Peter McGoron
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368bbb6e2b
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update generate_csr_locations
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2023-03-16 18:53:37 +00:00 |
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Peter McGoron
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50ef091578
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move preprocessed generation to common makefile
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2023-03-16 16:32:03 +00:00 |
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Peter McGoron
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55fc252382
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pass yosys
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2023-03-15 17:08:55 -04:00 |
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Peter McGoron
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fbbd41c95e
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codegen
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2023-03-15 14:57:22 -04:00 |
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Peter McGoron
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ca8078f9d6
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quick hack: pre-prepreprocess verilog files
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2023-03-15 18:47:20 +00:00 |
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Peter McGoron
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411c0c52c1
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add control_loop_cmds header generators
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2023-03-15 18:30:30 +00:00 |
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Peter McGoron
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953e42b80c
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change control_loop to m4 scripts, add common makefile
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2023-03-15 18:30:08 +00:00 |
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Peter McGoron
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7af907ffb4
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soc.py: fix syntax errors
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2023-03-15 03:04:27 -04:00 |
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Peter McGoron
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fefa6409cf
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soc.py: add missing waveform pins
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2023-03-15 06:30:59 +00:00 |
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Peter McGoron
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0f40b2cd95
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base: add new waveform pins
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2023-03-15 06:29:19 +00:00 |
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Peter McGoron
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4142a0a1b4
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simulate waveform.v
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2023-03-15 06:24:28 +00:00 |
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Peter McGoron
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c8f2cf1f7a
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spi_switch: fix dangling else
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2023-03-14 15:43:34 +00:00 |
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Peter McGoron
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90a49b6091
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test and simulate spi_switch
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2023-03-14 15:42:41 +00:00 |
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Peter McGoron
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36e5b964d5
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lint base.v
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2023-03-14 04:06:42 +00:00 |
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Peter McGoron
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d198273155
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add base.m4
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2023-03-14 01:40:17 +00:00 |
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Peter McGoron
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eadf374cd0
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lint waveform.v
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2023-03-10 22:59:26 +00:00 |
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Peter McGoron
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295eb8fad8
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add base.v
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2023-03-09 04:17:41 +00:00 |
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Peter McGoron
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89938a2ff6
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move autoapproach to possibly useful waveform module: not yet tested
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2023-03-03 18:30:00 +00:00 |