Commit Graph

139 Commits

Author SHA1 Message Date
Peter McGoron 5178594215 proper CSR location generation 2023-05-16 15:02:05 -04:00
Peter McGoron d0ec4cca9e convert differential outputs to single ended outputs 2023-05-11 16:47:24 -04:00
Peter McGoron 0a9125355f disable test clock by default 2023-05-11 15:31:52 -04:00
Peter McGoron e1d09495da update boothmul properly; add clean to make; hardware notes 2023-05-11 14:37:32 -04:00
Peter McGoron f0624bf664 adc debugging 2023-05-11 11:43:30 -04:00
Peter McGoron 15b8fcbe7e reset pins and test clock 2023-05-10 14:35:57 -04:00
Peter McGoron 40fd1ab6fe add debug clock 2023-04-20 15:20:42 -04:00
Peter McGoron ab4c23fa14 fix compile errors 2023-04-18 15:47:57 -04:00
Peter McGoron be4ed8afcf soc.py: fix compile errors 2023-04-13 12:20:19 -04:00
Peter McGoron e6c57ffa63 soc.py: cleanup CSR generation 2023-04-08 17:31:12 +00:00
Peter McGoron 92a140d736 generate_csr_locations: documentation 2023-04-08 16:47:59 +00:00
Peter McGoron a57b4ca91b generate_csr_locations.py: static const 2023-04-08 16:45:48 +00:00
Peter McGoron 5ff3ff675e COPYING: add A7-constraints.xdc 2023-04-08 16:40:16 +00:00
Peter McGoron 04b439a857 soc.py: documentation 2023-04-08 16:38:24 +00:00
Peter McGoron 27ada0d708 first pass at making correct memory accesses 2023-04-08 16:05:52 +00:00
Peter McGoron 9ff5576623 add missing .PHONY 2023-04-06 19:28:12 -04:00
Peter McGoron 79b71c7b0c manual 2023-04-06 19:14:01 -04:00
Peter McGoron e19a626945 dac, adc switch and documentation 2023-04-04 15:10:32 -04:00
Peter McGoron b7ca97695a make software build system cleaner 2023-04-04 12:24:58 -04:00
Peter McGoron 551f535513 compile 2023-04-04 12:04:06 -04:00
Peter McGoron 0f86a60510 compile verilog 2023-04-03 15:29:20 -04:00
Peter McGoron eceb844e87 kernel 2023-04-03 04:39:26 +00:00
Peter McGoron a26df53af5 add wf_running to generate_csr_locations.py 2023-04-03 03:13:54 +00:00
Peter McGoron 11f7cfd388 refactor soc.py base.v interface 2023-04-02 21:35:51 +00:00
Peter McGoron 69f16264dd add assertions 2023-04-02 21:25:19 +00:00
Peter McGoron 66ea3ca0ea waveform.v
fix potential hang in waveform.v
2023-04-02 21:20:26 +00:00
Peter McGoron a7da03f4b9 fix generate_csr_locations.py 2023-03-20 15:07:52 -04:00
Peter McGoron 908be977f5 merge 2023-03-20 17:59:37 +00:00
Peter McGoron f90348aff9 arty.xdc for synth test 2023-03-20 13:58:35 -04:00
Peter McGoron 0259523d20 add yosys synth test for control loop 2023-03-20 13:57:42 -04:00
Peter McGoron 93c92b9f55 add test scripts for synthesizing ram fifo 2023-03-20 13:57:15 -04:00
Peter McGoron 368bbb6e2b update generate_csr_locations 2023-03-16 18:53:37 +00:00
Peter McGoron 50ef091578 move preprocessed generation to common makefile 2023-03-16 16:32:03 +00:00
Peter McGoron 55fc252382 pass yosys 2023-03-15 17:08:55 -04:00
Peter McGoron fbbd41c95e codegen 2023-03-15 14:57:22 -04:00
Peter McGoron ca8078f9d6 quick hack: pre-prepreprocess verilog files 2023-03-15 18:47:20 +00:00
Peter McGoron 411c0c52c1 add control_loop_cmds header generators 2023-03-15 18:30:30 +00:00
Peter McGoron 953e42b80c change control_loop to m4 scripts, add common makefile 2023-03-15 18:30:08 +00:00
Peter McGoron 7af907ffb4 soc.py: fix syntax errors 2023-03-15 03:04:27 -04:00
Peter McGoron fefa6409cf soc.py: add missing waveform pins 2023-03-15 06:30:59 +00:00
Peter McGoron 0f40b2cd95 base: add new waveform pins 2023-03-15 06:29:19 +00:00
Peter McGoron 4142a0a1b4 simulate waveform.v 2023-03-15 06:24:28 +00:00
Peter McGoron c8f2cf1f7a spi_switch: fix dangling else 2023-03-14 15:43:34 +00:00
Peter McGoron 90a49b6091 test and simulate spi_switch 2023-03-14 15:42:41 +00:00
Peter McGoron 36e5b964d5 lint base.v 2023-03-14 04:06:42 +00:00
Peter McGoron d198273155 add base.m4 2023-03-14 01:40:17 +00:00
Peter McGoron eadf374cd0 lint waveform.v 2023-03-10 22:59:26 +00:00
Peter McGoron 295eb8fad8 add base.v 2023-03-09 04:17:41 +00:00
Peter McGoron 89938a2ff6 move autoapproach to possibly useful waveform module: not yet tested 2023-03-03 18:30:00 +00:00
Peter McGoron 05f8878751 add submodules and switch 2023-03-03 08:06:50 +00:00