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upsilon/firmware/rtl/control_loop
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Peter McGoron 0c10dc921c more work on control_loop 
* Make SPI masters internal to control loop module
* Rename commands to use I isntead of alpha
* add ADC value -> DAC value conversion to control loop math
 		2022-11-18 19:11:56 -05:00
..
Makefile Rewrite control_loop_math and simulate 2022-11-13 18:03:55 -05:00
boothmul.v Rewrite control_loop_math and simulate 2022-11-13 18:03:55 -05:00
boothmul_sim.cpp import updated boothmul 2022-11-11 22:14:50 -05:00
control_loop.v more work on control_loop 2022-11-18 19:11:56 -05:00
control_loop_cmds.vh more work on control_loop 2022-11-18 19:11:56 -05:00
control_loop_math.v more work on control_loop 2022-11-18 19:11:56 -05:00
control_loop_math_implementation.cpp Rewrite control_loop_math and simulate 2022-11-13 18:03:55 -05:00
control_loop_math_implementation.h Rewrite control_loop_math and simulate 2022-11-13 18:03:55 -05:00
control_loop_math_sim.cpp Rewrite control_loop_math and simulate 2022-11-13 18:03:55 -05:00
control_loop_sim.cpp changes 2022-11-11 21:57:58 -05:00
control_loop_sim_top.v more work on control_loop 2022-11-18 19:11:56 -05:00
intro.md integrate control_loop_math into control_loop 2022-11-17 19:07:21 -05:00
intsat.v add everything im working on 2022-09-16 18:01:34 -04:00
intsat_sim.cpp move simulators to the same directory of the simulated core 2022-10-17 00:45:19 -04:00
sign_extend.v Rewrite control_loop_math and simulate 2022-11-13 18:03:55 -05:00