2022-10-23 04:42:35 -04:00
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# Booth Multiplier
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Sequentially multiply two signed twos-compliment integers in
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Verilog using the [Booth Algorithm][1].
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[1]: https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm
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2023-04-21 13:39:18 -04:00
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This design (v1.0) has been sucessfully synthesized with F4PGA
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2022-10-29 22:20:15 -04:00
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(`5aafae65883e95e41de2d0294729662dbe0a34f5`) on a Digilent Arty A7-35T
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running at a clock speed of 100MHz. The test design is in `arty_test`.
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2022-10-23 04:42:35 -04:00
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## License
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2022-10-29 22:26:51 -04:00
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All source code is licensed under the CERN-OHL-W v2 or later, unless
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otherwise noted.
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2022-10-23 04:42:35 -04:00
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## Usage
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Set parameters `A1_LEN` and `A2_LEN` to the argument size of the
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first and second integer. Set `A2LEN_SIZ` equal to
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`floor(log2(A2_LEN) + 1)`.
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After inputting each integer, pulse `arm` and wait until `fin` goes
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high to retreive the output in `outn`.
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## Simulating
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Simulation is done with Verilator. Run `make`.
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