2017-12-27 16:21:55 -05:00
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2017-12-29 07:18:14 -05:00
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VERILOG = ../../../Murax.v toplevel.v toplevel_pll.v
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2017-12-27 16:21:55 -05:00
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generate :
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2019-01-03 14:07:38 -05:00
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(cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit")
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2017-12-27 16:21:55 -05:00
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2017-12-29 07:18:14 -05:00
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../../../Murax.v :
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2019-01-03 14:07:38 -05:00
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(cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit")
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2017-12-27 16:21:55 -05:00
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2018-01-21 09:39:10 -05:00
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../../../Murax.v*.bin:
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bin/toplevel.blif : ${VERILOG} ../../../Murax.v*.bin
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2017-12-27 16:21:55 -05:00
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mkdir -p bin
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2018-01-20 12:29:33 -05:00
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rm -f Murax.v*.bin
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cp ../../../Murax.v*.bin . | true
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2017-12-27 16:21:55 -05:00
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yosys -v3 -p "synth_ice40 -top toplevel -blif bin/toplevel.blif" ${VERILOG}
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bin/toplevel.asc : toplevel.pcf bin/toplevel.blif
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arachne-pnr -p toplevel.pcf -d 8k --max-passes 600 -P ct256 bin/toplevel.blif -o bin/toplevel.asc
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bin/toplevel.bin : bin/toplevel.asc
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icepack bin/toplevel.asc bin/toplevel.bin
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compile : bin/toplevel.bin
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time: bin/toplevel.bin
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icetime -tmd hx8k bin/toplevel.asc
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prog : bin/toplevel.bin
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iceprogduino bin/toplevel.bin
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sudo-prog : bin/toplevel.bin
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sudo iceprogduino bin/toplevel.bin
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clean :
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rm -rf bin
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2018-01-20 12:29:33 -05:00
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rm -f Murax.v*.bin
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