Hardware/VexRiscv
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101 commits 39 branches 2 tags 15 MiB
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4 commits

Author SHA1 Message Date
Charles Papon
11a63491bd Add YAML feature to store CPU info 2017-06-09 16:06:18 +02:00
Charles Papon
6b62d8da52 VexRiscv in Briey SoC is working on FPGA (including jtag debugging) 2017-05-29 21:17:14 +02:00
Dolu1990
fcb70a333f WIP 2017-03-11 00:34:49 +01:00
Dolu1990
130ed6345c boot 2017-03-08 22:17:48 +01:00