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VexRiscv
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56 Commits

Author SHA1 Message Date
Charles Papon 823ac353ff Add Murax SoC (very light, work on ice40) 2017-07-28 21:25:49 +02:00
Charles Papon a94343b98a Update to SpinalHDL 0.10.14 2017-06-17 15:15:19 +02:00
Charles Papon 11a63491bd Add YAML feature to store CPU info 2017-06-09 16:06:18 +02:00
Charles Papon 6b62d8da52 VexRiscv in Briey SoC is working on FPGA (including jtag debugging) 2017-05-29 21:17:14 +02:00
Dolu1990 fcb70a333f WIP 2017-03-11 00:34:49 +01:00
Dolu1990 130ed6345c boot 2017-03-08 22:17:48 +01:00