Hardware/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
Code Issues Projects Releases Packages Wiki Activity
195 commits 39 branches 2 tags 15 MiB
Commit graph

6 commits

Author SHA1 Message Date
Charles Papon
54b06e6438 Add SIMD_ADD regression and config (show case) 2017-08-08 18:19:02 +02:00
Dolu1990
59e09ce269 Exclude TCL from the repo 2017-07-16 18:24:28 +02:00
Charles Papon
f8678698fc Briey improve AXI FMax 
Faster debugginPlugin regression
 2017-06-11 11:52:59 +02:00
Charles Papon
5e9da0f27a Add self checked dhrystone test 2017-03-18 12:32:14 +01:00
Charles Papon
9fc82c9736 Pass verilator simple literal, add, jump 2017-03-12 20:12:40 +01:00
Dolu1990
130ed6345c boot 2017-03-08 22:17:48 +01:00