Dolu1990
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ce6fd6d0aa
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Add VexRiscvAxi4 demo
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2017-11-20 23:57:37 +01:00 |
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Dolu1990
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9f9ec823b8
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SpinalHDL 0.11.2
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2017-11-15 17:57:08 +01:00 |
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Dolu1990
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6c3fed3505
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SpinalHDL 0.11.1
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2017-11-15 16:44:42 +01:00 |
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Dolu1990
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ba42f71813
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pass VexRiscv regressions
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2017-10-30 14:29:25 +01:00 |
Charles Papon
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a37494f27f
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Set sbt organization to com.github.spinalhdl
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2017-08-01 20:43:15 +02:00 |
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Charles Papon
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823ac353ff
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Add Murax SoC (very light, work on ice40)
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2017-07-28 21:25:49 +02:00 |
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Charles Papon
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a94343b98a
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Update to SpinalHDL 0.10.14
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2017-06-17 15:15:19 +02:00 |
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Charles Papon
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11a63491bd
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Add YAML feature to store CPU info
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2017-06-09 16:06:18 +02:00 |
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Charles Papon
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6b62d8da52
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VexRiscv in Briey SoC is working on FPGA (including jtag debugging)
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2017-05-29 21:17:14 +02:00 |
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Dolu1990
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fcb70a333f
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WIP
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2017-03-11 00:34:49 +01:00 |
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Dolu1990
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130ed6345c
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boot
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2017-03-08 22:17:48 +01:00 |