Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
1,165 Commits 39 Branches 2 Tags 15 MiB
Commit Graph

2 Commits

Author SHA1 Message Date
japm48 163611bd11
Murax on arty_a7: fix RAMB type on soc_mmi.tcl 2020-02-11 18:49:56 +01:00
sebastien-riou 2bcddd333d forced the commit of missing TCL files 2020-01-17 00:33:02 +01:00