a0a406e301
use intersphinx instead of adding submodules
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Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
2022-02-10 04:14:26 +01:00
747740a6b1
Add information about inverter logic in techmaps
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Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-09-28 11:30:12 +02:00
2db5d5beb6
Add technology mapping description
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Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-09-28 11:25:53 +02:00
391951918b
Replace VPR abstract with official VPR documentation
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-09-25 21:50:21 +02:00
c73f9c8c96
Add SymbiFlow toolchain description
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Describe the synthesis and place and route process.
Add short description of Yosys synthesis tool.
Signed-off-by: Robert Winkler <rwinkler@internships.antmicro.com>
2019-09-25 21:50:21 +02:00
Unai Martinez-Corral
Robert Winkler
Tomasz Michalak
Robert Winkler