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modules: fix tWTR regression on MT46H32M32

This commit is contained in:
Florent Kermarrec 2018-10-02 18:53:13 +02:00
parent ad0a1d4215
commit 48c17ce8a4
1 changed files with 1 additions and 1 deletions
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litedram/modules.py
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@ -170,7 +170,7 @@ class MT46H32M32(SDRAMModule):
nrows = 8192 nrows = 8192
ncols = 1024 ncols = 1024
# timings # timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(1, None), tCCD=(1, None), tRRD=None) technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=72, tFAW=None, tRC=None, tRAS=None)} speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=72, tFAW=None, tRC=None, tRAS=None)}