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Merge pull request #85 from antmicro/fix_databits 

PhySettings: set missing databits parameter for S6QuarterRateDDRPHY
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enjoy-digital 2019-06-13 16:55:11 +02:00 committed by GitHub
parent fef530366a 24851c9a3b
commit 67de3cee14
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litedram/phy/s6ddrphy.py
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@ -421,6 +421,7 @@ class S6QuarterRateDDRPHY(Module):
self.settings = PhySettings( self.settings = PhySettings(
memtype="DDR3", memtype="DDR3",
databits=databits,
dfi_databits=2*databits, dfi_databits=2*databits,
nranks=nranks, nranks=nranks,
nphases=nphases, nphases=nphases,