Merge pull request #85 from antmicro/fix_databits

PhySettings: set missing databits parameter for S6QuarterRateDDRPHY
2019-06-13 16:55:11 +02:00 · 2019-06-13 16:55:11 +02:00 · 67de3cee14
parent fef530366a 24851c9a3b
commit 67de3cee14
1 changed files with 1 additions and 0 deletions
--- a/litedram/phy/s6ddrphy.py
+++ b/litedram/phy/s6ddrphy.py
@ -421,6 +421,7 @@ class S6QuarterRateDDRPHY(Module):

        self.settings = PhySettings(
            memtype="DDR3",
+            databits=databits,
            dfi_databits=2*databits,
            nranks=nranks,
            nphases=nphases,