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gen: add l2_data_width to kwargs

This commit is contained in:
Florent Kermarrec 2020-01-13 17:31:17 +01:00
parent b77af48d50
commit c07f4a1f1b
1 changed files with 3 additions and 1 deletions
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2
litedram/gen.py
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@ -258,12 +258,14 @@ class LiteDRAMCore(SoCSDRAM):
kwargs["integrated_rom_size"] = 0
kwargs["integrated_sram_size"] = 0
kwargs["l2_size"] = 0
kwargs["l2_data_width"] = 32
kwargs["with_uart"] = False
kwargs["with_timer"] = False
kwargs["with_ctrl"] = False
kwargs["with_wishbone"] = (cpu_type != None)
else:
kwargs["l2_size"] = 0
kwargs["l2_data_width"] = 32
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, sys_clk_freq,