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1507 Commits

Author SHA1 Message Date
Florent Kermarrec ec6d2467c7 frontend/avalon: Add back cmd_fifo (and always go through it). 2023-06-01 13:07:09 +02:00
Florent Kermarrec 3d016b2ad5 frontend/avalon: Use same order on record connections (valid/ready/payload). 2023-06-01 09:58:33 +02:00
Florent Kermarrec 389ba8fc94 frontend/avalon: Reorder a bit and remove TODO. 2023-06-01 09:50:29 +02:00
Florent Kermarrec 8b790b79d9 frontend/avalon: Consider single access as a 1 word burst and simplify. 2023-06-01 09:48:35 +02:00
Florent Kermarrec e0b144eddd frontend/avalon: Merge BURST-WRITE/READ states. 2023-06-01 09:28:05 +02:00
Florent Kermarrec 60712547e5 frontend/avalon: Remove SINGLE-WRITE/SINGLE-READ states since no longer useful with Cmd/Data-path decoupling. 2023-06-01 08:57:02 +02:00
Florent Kermarrec 5a092dd4ed frontend/avalon: Decouple Cmd and Data-paths in BURST-READ (We don't need to wait rdata.valid to return to Idle). 2023-06-01 08:54:55 +02:00
Florent Kermarrec c3963a1887 frontend/avalon: Decouple Cmd and Data-paths in BURST-WRITE (We don't need to wait that wdata_fifo is empty to return to Idle). 2023-06-01 08:45:47 +02:00
Florent Kermarrec cc434c407b frontend/adapter: Add early_cmd_ready parameter to keep default behaviour to False but allow enabling it in Avalon Frontend. 2023-05-31 19:07:06 +02:00
Florent Kermarrec 1b7435c6d5 frontend/avalon: Clearly separate Data/Control-paths and add TODO. 2023-05-31 19:02:53 +02:00
Florent Kermarrec a86bd6c3d0 frontend/avalon: Remove cmd_fifo (not useful). 2023-05-31 18:39:28 +02:00
Florent Kermarrec 49f48130e7 frontend/avalon: Always go through wdata_fifo. 2023-05-31 18:02:12 +02:00
Florent Kermarrec 4a8b102c7e frontend/avalon: Remove downconvert specific logic (no longer required with LiteDRAMNativePortConverter improvement). 2023-05-31 16:54:56 +02:00
Florent Kermarrec 045c8da62e frontend/adapter/LiteDRAMNativePortDownConverter: Do early ack of user cmd. 
To better decouple cmd/data paths in user logic.
 2023-05-31 16:52:38 +02:00
Florent Kermarrec e6857b4912 frontend/avalon/SINGLE_WRITE: Remove writedata update and port.cmd.last (not useful). 2023-05-31 11:00:45 +02:00
Florent Kermarrec 94f8c5c258 frontend/avalon: Avoid byteenable clear (data) and clear cmd_ready_seen in START. 2023-05-31 10:52:48 +02:00
Florent Kermarrec c482eaa08e frontend/avalon: Improve decoupling in START state. 2023-05-31 10:45:26 +02:00
Florent Kermarrec 9befeb0761 frotend/avalon: Another simplifiation pass on start condition. 2023-05-31 10:03:50 +02:00
Florent Kermarrec 10837c6a53 frontend/avalon: Simplify start condition. 2023-05-31 09:21:14 +02:00
Florent Kermarrec 90a6cbfd6f frontend/avalon: First review pass to make codestyle more similar to other LiteX/LiteDRAM modules. 2023-05-31 08:54:44 +02:00
Hans Baier e446c06339
frontend/avalon: properly implement bursts (#340) 
frontend/avalon: properly implement bursts
 2023-05-31 08:14:52 +02:00
Chen 83a29b190d
Add support for clam shell topology (#332) 
Add clam shell topology support.
 2023-05-25 22:20:21 +02:00
Florent Kermarrec d8c327b2b1 ci: Increase similarities with LiteX CI. 2023-05-23 16:41:59 +02:00
Florent Kermarrec b452f09df6 frontend/avalon: Minor cosmetic fixes. 2023-05-23 14:57:36 +02:00
Hans Baier f1293eae1e
Avalon frontend for LiteDRAM (#337) 
Add initial Avalon MM frontend + tests.
 2023-05-23 14:52:05 +02:00
Florent Kermarrec d7df59560e setup.py: Prepare for 2023.04. 2023-05-07 20:47:47 +02:00
enjoy-digital e452da7a00
Merge pull request #330 from timkpaine/tkp/ci 
add manifest, uplift setup.py to pass twine checks
 2023-04-11 17:01:51 +02:00
Tim Paine ad00237fa2 fix typo in ci 2023-04-07 19:08:35 -04:00
Tim Paine 81203855a6 move up version 2023-04-07 19:06:45 -04:00
Tim Paine d7886c5fc5 add manifest, uplift setup.py to pass twine checks 2023-04-07 18:59:35 -04:00
enjoy-digital 6c8df7cc7b
Merge pull request #326 from trabucayre/gw2ddrphy_fix_warnings 
phy/gw2ddrphy: supressing warnings about unconnected and bit length.
 2023-02-08 19:12:01 +01:00
Gwenhael Goavec-Merou 895b653a96 phy/gw2ddrphy: supressing warnings about unconnected and bit length. 2023-02-08 18:26:54 +01:00
enjoy-digital 455305a3ed
Merge pull request #322 from antmicro/msieron/make-tests-parallel-safe 
Make tests safe to run in parallel
 2023-01-31 08:25:18 +01:00
Florent Kermarrec f94366c769 ci: Add help2man install for verilator compilation. 2023-01-20 19:14:17 +01:00
Florent Kermarrec 18f00151ed ci: Specify verilator sha1 (Build broken with recent versions). 2023-01-19 10:01:38 +01:00
Florent Kermarrec d95c1fc583 frontend/dma: Update omit signals in LiteDRAMDMAReader (Thanks @mohammadshahidzade). 2023-01-16 11:21:47 +01:00
Michal Sieron a912a88081 Make tests safe to run in parallel 
For example using pytest-parallel you can greatly reduce time it takes
to run all tests.

```
$ pytest --workers auto test
```

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 21:49:50 +01:00
enjoy-digital b749e10970
Merge pull request #321 from antmicro/msieron/sdram-hw-test 
frontend/bist: replicate LFSR output to fill the DRAM port
 2023-01-11 19:10:23 +01:00
Michal Sieron dad2c972f7 test/common: fix expected data for test_bist.py 
Expected data needs to be replicated to fill given data_width.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 17:13:52 +01:00
Michal Sieron 73c3ec6b68 frontend/bist: make LFSR output comb 
Otherwise first output after reset is 0.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 15:36:19 +01:00
Michal Sieron f466c5f1db frontend/bist: replicate LFSR output to fill DRAM port 
Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 15:36:19 +01:00
Michal Sieron 89581c1da7 gen: increase ROM size 
Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 15:36:19 +01:00
Florent Kermarrec 69b401dea1 test/test_init: Update. 2023-01-10 14:45:27 +01:00
enjoy-digital d17b021aa2
Merge pull request #320 from antmicro/msieron/sdram-spd 
init: Define `SDRAM_PHY_[DDR3|DDR4|...]` and `SDRAM_PHY_SUPPORTED_MEMORY`
 2023-01-10 09:39:12 +01:00
Michal Sieron 8fa325310a init: define SDRAM_PHY_SUPPORTED_MEMORY 
To use as a default value when one can't read SDRAM size from the SPD.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-09 16:03:09 +01:00
Michal Sieron 4c9f184566 init: define SDRAM_PHY_[DDR3|DDR4|...] 
Will allow to ifdef code specific to some memory types like SPD reads.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-09 16:03:09 +01:00
enjoy-digital 8339f54322
Merge pull request #319 from antmicro/msieron/fix-bist-errors 
frontend/bist: properly signal finished writes
 2023-01-05 22:21:23 +01:00
Michal Sieron f45ca410ad frontend/bist: properly signal finished writes 
Without it, software was resetting the generator too early and wrong
data was being written to the RAM.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-04 14:00:59 +01:00
Florent Kermarrec 3b2bcf91ed ci: Switch to ubuntu 22.04 and increase similarities with LiteX's CI. 2022-12-09 11:06:58 +01:00
Florent Kermarrec 6b00d1adce ci: Install RISC-V GCC with litex_setup.py. 2022-12-08 21:57:50 +01:00