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1507 Commits

Author SHA1 Message Date
Piotr Binkowski 2c2b73442a phy/lpddr5: add PHY for series 7 2021-10-26 12:22:30 +02:00
Piotr Binkowski e4e2aa49b8 phy/lpddr4: extract io helpers to a separate class 2021-10-26 12:22:30 +02:00
Jędrzej Boczar a4fb1a633a phy/lpddr5: do not use dataclasses for Python 3.6 compatibility 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 9795d6902c phy/lpddr5/sim: partially disable DFITimingsChecker when --disable-delay is on 
With --disable-delay the software won't insert delays in between
commands during memory training which results in DFITimingsChecker
reporting timing violations. With this change we disable
DFITimingsChecker until software completes memory initialization.
 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 247641a353 phy/lpddr5/sim: don't check timings when --disable-delay is used 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 0009f6d2be phy/lpddr5/sim: show timing progress when logging timing violation 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 9ef6e4b444 phy/lpddr5/sim: add DFITimingsChecker 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 91f14b2414 phy/lpddr5/sim: add option to wrap the PHY with DFIRateConverter 2021-10-26 12:22:30 +02:00
Jędrzej Boczar e329545ea6 phy/lpddr5/sim: make wr/rd timings correct for both CKR=4 and 2 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 2c8a06ed00 phy/lpddr5/sim: reset FSM to initial state when RESET_n is pulled low 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 59467f8ae6 phy/lpddr5: add a way to send actual NOP instead of DESELECT 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 9c49d80e6b phy/lpddr5: add power-up initialization sequence 2021-10-26 12:22:30 +02:00
Jędrzej Boczar c795bafda7 phy/lpddr5/sim: add verification of initialization sequence 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 27da8c5c43 phy/lpddr5/sim: update mode register reset values 2021-10-26 12:22:30 +02:00
Jędrzej Boczar e39aec4b7e phy/lpddr5/sim: fix command timeouts calculation 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 7f742c7fde phy/lpddr5/sim: handle data masking during masked-write 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 26cbb700bc phy/lpddr5/sim: update delay for read data, add basic CAS handler 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 4e974738d1 phy/lpddr5: fix column address encoding/decoding 2021-10-26 12:22:30 +02:00
Jędrzej Boczar a015b66e4f phy/lpddr5: fix write latency 2021-10-26 12:22:30 +02:00
Jędrzej Boczar e906c82ea2 phy/lpddr5/sim: debug serialization in gtkwave savefile 2021-10-26 12:22:30 +02:00
Jędrzej Boczar bfb8aaf44c phy/lpddr5/sim: clean up write burst handling and implement read bursts 2021-10-26 12:22:30 +02:00
Jędrzej Boczar b8616fdfac phy/lpddr5/sim: make adding module loggers simpler 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 5544875e1d phy/lpddr5/sim: fix SimLogger timestamps 
Timestamps were completely wrong for WCK as it is disabled
until the first write command and has varying frequency.
Now we use another clock which is always on to calculate time.
 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 592ed9cac4 phy/lpddr5/sim: add initial data commands handling 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 6366a02389 phy/sim_utils: fix log level NONE not working 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 914d018cf8 phy/sim_utils: support low wait times (0/1) in PulseTiming 2021-10-26 12:22:30 +02:00
Jędrzej Boczar f9a11ea5ce phy/lpddr5: start implementing DRAM simulator 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 2671508a11 phy/lpddr5: add simulation SoC 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 261f3dcd63 phy/lpddr5: add simulation phy 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 7cdf0e11ca phy/lpddr5: add unit tests 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 68a0ac7e88 phy/lpddr5: add command adaptaion and base phy implementation 2021-10-26 12:22:30 +02:00
Florent Kermarrec 2b0f806c96 ci: Increase similarities with LiteX CI. 2021-10-26 12:15:39 +02:00
Florent Kermarrec f537b5dd52 phy/s7ddrphy: Fix DDR2 case. 2021-10-18 15:33:56 +02:00
enjoy-digital 3202bc6acd
Merge pull request #277 from antmicro/acom/s7phy_ddr4 
phy: s7: add DDR4 memtype as well
 2021-10-18 13:35:15 +02:00
Florent Kermarrec 1d5192f572 litedram_gen/fifo: Avoid unnecessary get_port(). 2021-10-08 08:52:50 +02:00
Florent Kermarrec e1defa2687 litedram_gen: Fix rate for 7-Series. 2021-10-07 16:22:40 +02:00
Florent Kermarrec 1c59e77302 litedram_gen/add_sdram: Remove origin: no longer required. 2021-10-07 16:20:23 +02:00
Florent Kermarrec f0a2f40a86 litedram_gen: Compute rate based on type of PHY (DDR3 rate is 1:2 with ECP5DDRPHY). 2021-10-07 15:41:51 +02:00
Florent Kermarrec 0bb3bff8af litedram_gen: Set default csr_data_width to 32 (similar to LiteX). 2021-10-07 15:28:36 +02:00
Florent Kermarrec 6b0a35b309 litedram_gen: Add rst signal to CRG and use it as PLL reset. 2021-10-07 14:00:53 +02:00
Florent Kermarrec ba0012f881 examples/versa_ecp5: Fix memtype. 2021-10-07 13:44:36 +02:00
Florent Kermarrec 460dcc0a9e gen/init: Simplify Electrical Settings collection (and make them optional with litedram_gen). 
When not specified in litedram_gen, the default settings will be used.
 2021-10-07 13:44:25 +02:00
enjoy-digital e1512553f8
Merge pull request #280 from antonblanchard/ecp5-fixes 
Fix a few issues with ECP5 standalone generator
 2021-10-07 08:43:12 +02:00
Florent Kermarrec ef8db14967 frontend/fifo: Fix data_width_ratio == 1 case. 2021-10-06 19:07:44 +02:00
Florent Kermarrec 136be83749 frontend/fifo: Revisit DRAM state to avoid deadlock situations when port_data_width != port_address_width. 2021-10-06 18:05:48 +02:00
Florent Kermarrec 1598b2733a frontend/fifo: Expose base/depth in bytes instead of DRAM's words. 2021-10-06 14:47:34 +02:00
Florent Kermarrec f3d01ce98c litedram_gen: Expose ControllerSettings to user (and make cmd_buffer_length optional). 2021-10-06 14:31:57 +02:00
Anton Blanchard 99f53fcd1f phy/ecp5ddrphy: set cmd_delay from YAML config 2021-10-03 20:03:11 +11:00
Anton Blanchard e0cf7d579e phy/ecp5ddrphy: set rtt_nom/rtt_wr/ron from YAML config 2021-10-03 20:02:51 +11:00
Florent Kermarrec ce72e5b3fe modules: Add MT40A2G8/MT40A2G16. 2021-10-02 14:51:46 +02:00