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1507 Commits

Author SHA1 Message Date
Florent Kermarrec 894c7fb49e phy/model: Let the model pick default settings when settings is set to None (In this case, data_width needs to be provided). 2021-07-08 09:09:05 +02:00
Florent Kermarrec daf2cb7d39 phy/model: Integrate sdram_module_nphases/get_sdram_phy_settings from litex_sim. 2021-07-08 09:02:13 +02:00
Florent Kermarrec a3aa4907f1 phy/lpddr4/simsoc: Change cpu_variant to lite and revert commented test_lpddr4_sim_x2rate_no_cache. 
(see #255).
 2021-07-02 09:24:11 +02:00
Florent Kermarrec a11d1b870d litedram_gen: Remove device limitation on GENSDRPHY/ECP5DDRPHY. 
By specifying FPGA device in .yml files for configs requiring  it.
 2021-07-02 09:15:42 +02:00
Florent Kermarrec 317072a198 litedram_gen: Add initial SDRAM support (with ULX3S example). 2021-07-02 09:01:31 +02:00
enjoy-digital 83d18f48c7
Merge pull request #257 from antmicro/jboc/lpddr5-split 
LPDDR4 code refactor
 2021-06-29 13:04:48 +02:00
Florent Kermarrec afd00f7873 bench/common/bench_test: Improve UART dump speed. 2021-06-29 12:38:44 +02:00
Florent Kermarrec e90aa5a4d5 bench/targets: Minor CRG cleanups. 2021-06-29 12:36:02 +02:00
Jędrzej Boczar 405cf8a8a5 phy/utils: add HoldValid stream primitive 2021-06-22 11:41:44 +02:00
Jędrzej Boczar 34fbe01a78 test/phy_common: make chunk size in PadsHistory summary configurable 2021-06-22 11:41:44 +02:00
Jędrzej Boczar eb6e7a1514 test/lpddr4: move dfi_data_to_dq to common code 2021-06-22 11:41:44 +02:00
Jędrzej Boczar fcda73a175 test/phy_common: simplify calls to run_simulation 2021-06-22 11:41:44 +02:00
Jędrzej Boczar 13cdbc0ed9 phy/utils: ConstBitSlip: allow for different bitrate relation of CA vs CS 2021-06-22 11:41:44 +02:00
Jędrzej Boczar da769094fd phy/lpddr4: fix edge case error with CommandsPipeline ignoring a command 
Command was being ignored when it occurred on the last phase and
the next command would invalidate the first phase. Now it is fixed
and a regression test is included. A fix in ConstBitSlip has been added
due to wrong Verilog being generated with cycles=1, register=False.
 2021-06-22 11:40:51 +02:00
Jędrzej Boczar baf9c07858 phy/utils: improve ConstBitSlip: 
* optional register=False to decrease latency by 1 cycle
* require explicit `cycles` as it influences latency (min_cycles
  still can be used)
* add unit tests
 2021-06-21 14:43:49 +02:00
Jędrzej Boczar 4a96be86c0 test/lpddr4: move run_simulation wrapper to phy_common.py 2021-06-21 14:43:49 +02:00
Jędrzej Boczar 4b16dd994a phy/utils: automatically determine number of cycles in ConstBitSlip 2021-06-21 14:43:49 +02:00
Jędrzej Boczar 1543fa4ace phy/lpddr4: extract common test helpers for use when testing other PHYs 2021-06-21 14:43:49 +02:00
Jędrzej Boczar 721b6f874b phy/lpddr4: make simphy serialization cleaner and easier to read 2021-06-21 14:43:49 +02:00
Jędrzej Boczar 47e8a59511 phy/lpddr4: extract SimulationPads and use it as a base class 2021-06-21 14:43:49 +02:00
Jędrzej Boczar 060dbcc70d phy/lpddr4: extract command serialization logic into separate class 2021-06-21 14:43:49 +02:00
Jędrzej Boczar 5ccf3b57cc phy/lpddr4: use databits//8 explicitly 2021-06-21 13:22:15 +02:00
Jędrzej Boczar 8e563239f9 phy/lpddr4: extract common utilities 2021-06-21 13:22:15 +02:00
Jędrzej Boczar badf94e403 phy/lpddr4: move common utils up a directory 2021-06-21 13:22:15 +02:00
Jędrzej Boczar 1eecd297a1 phy/lpddr4: remove use of deprecated soc_sdram_args 2021-06-21 13:22:15 +02:00
Florent Kermarrec d16aaa7456 frontend/ecc: Add optional Write errors detection (checking granularity). 
Write granularity has been recently reduced from DRAM's full burst data-width to DRAM's data-width.
This can avoid read-modify-write pattern from User logic, but we also need to be sure
the User logic will not generate partial access or adjust the granularity correctly.

The new with_we_error_detection paramter can be set to True to enable Write granularity errors
and can ease debug.
 2021-06-09 09:27:58 +02:00
Florent Kermarrec 5ce6bf7824 frontend/ecc: Add burst_cycles parameter (ease understanding and will be required if used on non 1:4 DDR PHYs). 2021-06-08 17:28:46 +02:00
Florent Kermarrec c5d70114b5 frontend/ecc: Reduce write byte enable granularity from DRAM's full burst data-width to DRAM's data-width. 
Also add comments.
 2021-06-08 16:59:29 +02:00
Florent Kermarrec 377d6fac6c test/test_lpddr4: Disable failing test. 2021-06-08 15:07:53 +02:00
Florent Kermarrec 2fcc6fe552 test/test_ecc: Update. 2021-06-08 15:07:39 +02:00
Florent Kermarrec 8b606cd05a frontend/ecc/LiteDRAMNativePortECCW: Only set source.we when sink has at least one valid byte to write. 
Write access with sink.we bits all set to 0 can happen when converters are used
in the user logic.
 2021-06-04 18:31:09 +02:00
enjoy-digital 3f88eb9a43
Merge pull request #253 from gsomlo/gls-fix-gcc-warn 
fix gcc warning: function used but not defined
 2021-05-28 08:28:43 +02:00
Gabriel Somlo dc6cb89737 also remove 'static' from cdelay() declarations in test suite 2021-05-26 12:09:26 -04:00
Gabriel Somlo e2b5602acf fix gcc warning: function used but not defined 
The 'cdelay()' function is defined in LiteX 'liblitedram', so we
should not be using 'static' to declare it before calling it from
other C source files.
 2021-05-26 10:35:28 -04:00
Florent Kermarrec b0bbe8aa75 frontend/dma/LiteDRAMDMAWriter: Fix refactoring fsm state typo. 2021-05-26 15:18:04 +02:00
Florent Kermarrec b8cd26fa52 test/refefence: Update. 2021-05-18 11:26:40 +02:00
Florent Kermarrec 0877a81b4b test/test_init: Add simple way to update references. 2021-05-18 11:26:19 +02:00
enjoy-digital afbb229308
Merge pull request #252 from antmicro/jboc/lpddr4-inc-freq 
init: generate sdram_phy.h in a way that allows to include it in multiple units
 2021-05-18 10:27:39 +02:00
Jędrzej Boczar 282c208b63 init: generate sdram_phy.h in a way that allows to include it in multiple units 2021-05-13 18:54:01 +02:00
enjoy-digital 762da8034d
Merge pull request #250 from andrewb1999/adapter-fix 
Only update UpConverter sel when input valid
 2021-05-03 16:59:55 +02:00
enjoy-digital feba854c0b
Merge pull request #249 from andrewb1999/master 
Fix adapter reverse typo
 2021-05-03 16:49:59 +02:00
Andrew Butt e97ff4aaa0 Fix adapter sel 
Signed-off-by: Andrew Butt <andrewb1999@gmail.com>
 2021-05-01 17:42:07 -04:00
Andrew Butt 99990b9eae Fix adapter reverse typo 
Signed-off-by: Andrew Butt <andrewb1999@gmail.com>
 2021-04-30 11:49:20 -04:00
Florent Kermarrec 63358ee666 test/reference: Update. 2021-04-28 18:21:27 +02:00
enjoy-digital 8a4311ba40
Merge pull request #248 from antmicro/jboc/lpddr4-init 
init/lpddr4: make some settings configurable via phy_settings
 2021-04-28 17:58:49 +02:00
Florent Kermarrec 6755c8438f frontend/wishbone: Fix refactoring typos (thanks jfng). 2021-04-28 17:55:18 +02:00
Florent Kermarrec 981d5a077b init: Disable DQ-DQS training on Ultrascale(+) for now (requires more testing). 2021-04-28 17:54:25 +02:00
Jędrzej Boczar 3cdce6ca53 init/lpddr4: make some settings configurable via phy_settings 2021-04-28 15:05:33 +02:00
enjoy-digital c139f9d3d4
Merge pull request #247 from andrewb1999/master 
Fix UpConverter reversed write mask
 2021-04-27 18:19:32 +02:00
Florent Kermarrec bd80053ebf frontend/wishbone: Rewrite/Simplify using an FSM (as it was originally) and also add Abort support. 2021-04-27 16:08:15 +02:00