Florent Kermarrec
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426ae23d2a
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examples/litedram_gen: add sdram_module_speedgrade parameter
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2018-10-01 11:48:15 +02:00 |
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Florent Kermarrec
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30c32f557c
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example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :)
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2018-09-25 10:40:24 +02:00 |
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Florent Kermarrec
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37f1decfb2
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multirank: one cs_n/cke/odt/clk per rank
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2018-09-09 14:32:15 +02:00 |
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Florent Kermarrec
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8ddc6c735d
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drive odt of all ranks, fixes and test non regression with 1 rank
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2018-09-09 01:52:24 +02:00 |
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Florent Kermarrec
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cc481be81f
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examples: add sdram_rank_nb and user_ports_id_width
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2018-09-07 17:55:46 +02:00 |
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Florent Kermarrec
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1652ab95c8
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examples/litedram_gen: fix address width of axi ports (addressing in bytes not words)
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2018-09-05 09:13:47 +02:00 |
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Florent Kermarrec
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1e64b7f492
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examples/litedram_gen: expose resp signals to user
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2018-09-05 08:51:27 +02:00 |
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Florent Kermarrec
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de69867995
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examples/litedram_gen: expose last signals to user
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2018-09-05 08:32:49 +02:00 |
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Florent Kermarrec
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e8bd782999
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examples/litedram_gen: expose burst signals to user
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2018-09-05 08:31:57 +02:00 |
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Florent Kermarrec
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5e4dca9a7b
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add examples with standalone cores for arty and genesys2
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2018-08-31 23:20:47 +02:00 |