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Author SHA1 Message Date
055cbdbc43 tRRD is specified incorrectly. 2018-10-11 16:57:24 -04:00
acef5f523b Fix issue where we ignore important timing parameters. 2018-10-11 16:56:36 -04:00
08afc9d8bc Fix incorrect activate timing bugs 2018-10-11 04:17:49 -04:00
825a82a3ea Fix for 1:4 (UNTESTED) 2018-10-08 13:58:05 -04:00
63dcd7e92b Register the mux arbitrator 2018-10-08 13:53:29 -04:00
7aa5457b09 Fix incorrect logic in the rd/wr decision 2018-10-05 00:54:02 -04:00
6275f6cc59 Revert "Further timing improvements" + Bug fixes 
This reverts commit 9475f9258e.
 2018-10-04 00:03:12 -04:00
6b99c7f92b cleanup & timing 2018-10-03 11:29:17 -04:00
c1f44e2286 Use tXXDController everywhere (better timing). Also fix a bug in the previous commit for cmd.is_activate 2018-10-02 22:48:36 -04:00
8b01871986 Reduce timing contention on cmd.we pin by adding is_activate 2018-10-02 21:56:14 -04:00
ad6ff361cb Merge branch 'write_latency' into bank_reordering 2018-10-02 16:25:10 -04:00
3bb04f278a Add a latency parameter so wdata can be registered 2018-10-02 16:24:33 -04:00
48d8720662 Merge branch 'master' of https://github.com/enjoy-digital/litedram into bank_reordering 2018-10-02 15:19:40 -04:00
Florent Kermarrec
48c17ce8a4 modules: fix tWTR regression on MT46H32M32 2018-10-02 18:53:13 +02:00
Florent Kermarrec
ad0a1d4215 modules: improve timings definition (keep retro-compatibility with previous definitions) 2018-10-02 10:32:45 +02:00
Florent Kermarrec
5b02791580 modules: add tCCD to all modules 2018-10-02 08:41:48 +02:00
Tim 'mithro' Ansell
6c7a804986 Adding tCCD for DDR2 modules. 2018-10-01 19:01:12 -07:00
208f5562d1 Merge branch 'master' of https://github.com/enjoy-digital/litedram 2018-10-01 19:36:05 -04:00
69eaf844e8 Fix DDR2 and below compilation failure 2018-10-01 19:35:20 -04:00
9475f9258e Further timing improvements 2018-10-01 19:33:21 -04:00
76a3e45694 Register bank machine commands to improve timing 2018-10-01 15:07:31 -04:00
1c8bba06b2 More efficient read/write turnaround, and let banks start their row changes as early as possible 2018-10-01 14:12:32 -04:00
Florent Kermarrec
41a8a246b6 modules: express tFAW in ns 2018-10-01 19:41:30 +02:00
Florent Kermarrec
70620689a0 modules: split DDR3 in 2 categories: Chips and SO-DIMMs 2018-10-01 12:17:50 +02:00
Florent Kermarrec
0f46dc4ab7 modules: add DDR3-800 timings for MT41J128M16 and use it on arty example 2018-10-01 11:59:54 +02:00
Florent Kermarrec
426ae23d2a examples/litedram_gen: add sdram_module_speedgrade parameter 2018-10-01 11:48:15 +02:00
Florent Kermarrec
1bc016cf6c test: add test_examples 2018-10-01 11:29:08 +02:00
Florent Kermarrec
f7f8169883 test: update downconverter/upconverter 2018-10-01 11:18:54 +02:00
Florent Kermarrec
8de1d91eac core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) 2018-10-01 11:18:39 +02:00
5cae0993bb Start of in-bank reordering. Note: does not detect address conflicts 2018-09-30 22:41:26 -04:00
70516c40bf Merge branch 'master' of https://github.com/enjoy-digital/litedram 2018-09-30 22:17:45 -04:00
Florent Kermarrec
58209708e7 frontend/crossbar: fix #49 2018-09-29 20:09:07 +02:00
71f78d953e Fix reordering controller rejecting all commands 2018-09-29 13:52:20 -04:00
8f14211f00 Account for CWL in write to read timing 2018-09-29 12:39:40 -04:00
Florent Kermarrec
5fb8afe7e5 frontend/axi: omit bank in rdata connect 2018-09-28 23:44:12 +02:00
enjoy-digital
06ca53d2b2
Merge pull request #48 from enjoy-digital/staging 
Staging
 2018-09-28 23:29:41 +02:00
enjoy-digital
5a4d063f64
Merge branch 'master' into staging 2018-09-28 23:29:24 +02:00
Florent Kermarrec
5984eaa6da core: change api for out-of-order. (with_reordering passed to controller and not ports). 
We are not going to mix in-order/out-of-order ports
 2018-09-28 23:16:54 +02:00
Florent Kermarrec
6e10daed58 core/bankmachine/write to precharge: indicate that AL=0 2018-09-25 21:04:19 +02:00
enjoy-digital
869c8ee618
Merge pull request #46 from enjoy-digital/WritePrechargeFix 
Update the write-to-precharge timings so it works with 1:2
 2018-09-25 20:59:36 +02:00
0405f4156d Update the write-to-precharge timings so it works with 1:2 2018-09-25 12:06:19 -04:00
Florent Kermarrec
30c32f557c example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) 2018-09-25 10:40:24 +02:00
Florent Kermarrec
2a3cacb967 core/bankmachine: minor cleanup on trc/tras 2018-09-23 21:19:17 +02:00
enjoy-digital
42ccf05e15
Merge pull request #45 from enjoy-digital/tRAS_FIX 
Implement tRAS
 2018-09-23 22:19:58 +02:00
John Sully
79b1421878 Auto precharge is too pessimistic, it will wait on its own for a valid time to execute 2018-09-23 20:55:24 +02:00
John Sully
177d7393f9 Implement tRAS 2018-09-23 19:42:46 +02:00
enjoy-digital
59020270af
Merge pull request #44 from enjoy-digital/tRC_Fix 
This adds support for tRC timing parameters
 2018-09-23 18:09:15 +02:00
John Sully
5f6b85703d This adds support for tRC timing parameters 2018-09-23 17:56:07 +02:00
enjoy-digital
1777720a0c
Merge pull request #42 from enjoy-digital/HalfRateSequentialFix 
We wait an extra cycle for no reason
 2018-09-23 15:04:42 +02:00
John Sully
06c8c2afcf The actual fix 2018-09-23 11:32:49 +02:00