f0be039a34
test: add option to use sdram timing verifier in benchmarks
2020-02-17 14:35:15 +01:00
b7ed91d9f0
test: suppress info log messages in benchmark runner
2020-02-17 13:14:52 +01:00
5719b77ae8
phy: use new BitSlip module with reduced latency (-1 sys_clk cycle)
2020-02-17 12:40:46 +01:00
d646e2a6a7
common: add BitSlip module (with reduced latency)
2020-02-17 12:40:06 +01:00
ef0086e720
phy/model: fix memory addressing issues in some configurations
2020-02-17 12:21:31 +01:00
c6cc0e068d
test: keep benchmark failures in data frame and filter out when needed
2020-02-17 09:07:13 +01:00
bba49f2df8
test: add generation of html benchmarks summary
2020-02-17 09:07:13 +01:00
9083822a74
phy/model: change timing checker parameter, use a verbosity parameter
2020-02-16 16:04:11 +01:00
95b827d435
Merge pull request #142 from antmicro/updated-trefi-verifier
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Update tREFI verifier
2020-02-15 16:32:41 +01:00
0ba31d6d8e
frontend/bist: regroup random_data/random_addr in the same CSRStorage to keep software retro-compatibility
2020-02-15 16:24:59 +01:00
fc27b21a99
frontend/bist: fix LiteDRAMBISTChecker random_data/addr
2020-02-15 16:07:48 +01:00
e0b4278e6f
frontend/bist: set run to 1 by default to keep similar default behaviour than before adding run/ready.
2020-02-15 16:03:45 +01:00
13d0350436
phy/model: add refresh postponing checks
2020-02-14 16:12:22 +01:00
93e220741e
phy/model: check tREFI in 64ms time slices
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This modifies the verifier to by default only check if overall average tREFI length was correct in a 64ms time slice.
Old method that enforces the delay between each REF command is now only used when verbose logging is enabled.
2020-02-14 14:59:34 +01:00
8a46b71411
phy/model: cleanup indent, avoid too long lines.
2020-02-13 17:25:37 +01:00
fc06a864e5
phy/model: use " instead of ' (as we are usually doing)
2020-02-13 17:02:55 +01:00
8594e12b3a
phy/model: update TODO
2020-02-13 16:57:47 +01:00
5d9b28aa10
Merge pull request #138 from antmicro/dfi-timings-checker
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phy/model: add basic timing violation checker
2020-02-13 16:52:33 +01:00
94aaa06bce
phy/model: add option to disable timings checker and enable verbose output
2020-02-13 14:22:35 +01:00
d71764d47e
Merge pull request #141 from antmicro/jboc/benchmark
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Benchmark: reduce disk usage when running benchmarks in parallel
2020-02-13 14:00:17 +01:00
804e74985c
phy/model: add basic timing violation checker
2020-02-13 13:54:27 +01:00
dd12a78587
test: reduce disk usage when running benchmarks in parallel
2020-02-13 10:30:48 +01:00
4febb2a6aa
Merge pull request #140 from antmicro/jboc/benchmark
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Benchmark: use variable number of BIST generators/checkers
2020-02-12 16:56:31 +01:00
5cd33f490f
test: update benchmark configuration generator
2020-02-12 15:42:50 +01:00
4f613b5b00
test: add number of generators/checkers to benchmark runner, update metrics
2020-02-12 14:40:33 +01:00
edf4ddb2f2
test: add option to use multiple BIST generators/checkers
2020-02-12 14:40:33 +01:00
354139959a
fix: code formatting
2020-02-12 14:40:33 +01:00
38fe8a81dd
Merge pull request #139 from enjoy-digital/travis-ci
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travis-ci: avoid use of conda (setup is simple enough to avoid it)
2020-02-12 10:47:18 +01:00
8316ed3a47
travis-ci: avoid use of conda (setup is simple enough to avoid it)
2020-02-12 10:28:37 +01:00
cd4e007a27
Merge pull request #128 from antmicro/linux-ci
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Add simulations to Travis CI
2020-02-12 08:23:40 +01:00
0904d8bc4d
Merge pull request #137 from antmicro/jboc/benchmark
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Benchmark: add simultaneous Write/Read and random address generation
2020-02-12 08:13:49 +01:00
45633e55b5
test: update BIST generator and checker tests
2020-02-11 14:24:02 +01:00
409b9922ea
test: add random address generation in benchmarks
2020-02-11 13:11:06 +01:00
abf6d1c3d6
test: add random address generation to BIST
2020-02-11 13:10:10 +01:00
6744cf649c
test: add handling of alternating write/read to benchmark runner
2020-02-11 13:10:04 +01:00
e16118abfd
test: fix: use of undeclared variable
2020-02-11 12:13:37 +01:00
ff435fd26e
test: add option to run benchmarks with alternating write/read
2020-02-11 12:06:45 +01:00
6093f2012e
test: add run/ready signals to BIST modules
2020-02-11 11:45:01 +01:00
831eadcc6d
travis: add simulation tests
2020-02-11 02:22:25 +01:00
ca17cfd83d
frontend/wishbone: round port_data_width to lowest power of 2 (required for ECC cases)
2020-02-10 09:56:36 +01:00
ad173d69fb
Merge pull request #136 from antmicro/jboc/benchmark
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Benchmark: use Memory instead of Case for custom access pattern
2020-02-08 09:27:27 +01:00
cf5939f09e
test: use Memory instead of Case for custom access pattern
2020-02-07 14:58:33 +01:00
ab8661405a
Merge pull request #135 from antmicro/jboc/benchmark
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Improve speed of benchmark runner
2020-02-07 12:41:29 +01:00
9148400ef5
test: fix typo, add note about limitations
2020-02-07 12:20:43 +01:00
2825c080a9
test: fix problem with plot labels overlapping for large number of benchmarks
2020-02-07 09:52:31 +01:00
08fd2960d0
Merge pull request #131 from antmicro/jboc/benchmark
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Allow testing custom access patterns
2020-02-06 18:12:35 +01:00
77541c3670
test: avoid instantiating LiteDRAMBenchmarkSoC to speed up summary generation
2020-02-06 15:08:01 +01:00
027034db49
test: add option to run benchmarks as parallel jobs
2020-02-06 15:07:55 +01:00
62a5473ecd
test: update script for generating benchmark configurations
2020-02-06 13:35:34 +01:00
c2051df1c3
Merge pull request #132 from antmicro/modules-fix-syntax-error
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modules: MT18KSF1G72HZ: use float as tWR value
2020-02-06 09:43:43 +01:00
Piotr Binkowski
Jędrzej Boczar
Florent Kermarrec
Mariusz Glebocki