Florent Kermarrec
|
6256031d51
|
bench: Update build directories and add rst in CRG (triggered on CPU reboot).
|
2021-04-22 14:57:13 +02:00 |
|
Florent Kermarrec
|
c2a779df46
|
bench: Update test targets (add_csr no longer required).
|
2021-04-19 13:40:17 +02:00 |
|
Florent Kermarrec
|
5cd192a708
|
bench: Remove soc_sdram import (No longer useful and deprecated).
|
2021-03-30 08:49:54 +02:00 |
|
Florent Kermarrec
|
3f9759b83b
|
bench/xcu1525: Update build directories.
|
2021-03-12 10:59:06 +01:00 |
|
Florent Kermarrec
|
df5f555842
|
bench: Update with recent changes.
|
2021-03-12 10:25:11 +01:00 |
|
Florent Kermarrec
|
a87c468afa
|
bench: use --sys-clk-freq=xy to reconfigure frequency and fix Ultrascale.
|
2020-12-10 19:06:19 +01:00 |
|
Florent Kermarrec
|
75f87538a5
|
bench: use common load_bios function.
|
2020-12-10 11:21:21 +01:00 |
|
Florent Kermarrec
|
ea63480253
|
bench/targets: add identifier.
|
2020-12-10 11:12:45 +01:00 |
|
Florent Kermarrec
|
c472499131
|
bench/targets: add optional analyzer on all test targets.
|
2020-12-10 08:44:35 +01:00 |
|
Florent Kermarrec
|
c83e10dafe
|
bench: cleanup clocking on Ultrascale targets.
|
2020-11-06 16:14:22 +01:00 |
|
Florent Kermarrec
|
4d1f4d5052
|
bench/xcu1525: use specific output_dir per channel (to allow // build of bitstreams for the different channels).
|
2020-11-06 10:47:26 +01:00 |
|
Florent Kermarrec
|
0890908a63
|
bench/xcu1525: rename ddram_channel arg to channel (since it's a dram specific design).
|
2020-11-06 10:36:56 +01:00 |
|
Florent Kermarrec
|
5cfdf77654
|
bench/targets: simplify BIST integration using new add_sdram with_bist parameter.
|
2020-11-06 10:34:26 +01:00 |
|
Florent Kermarrec
|
51b8eb1f82
|
bench: add xcu1525 target.
|
2020-10-29 19:11:23 +01:00 |